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| m s p 4 4 x 8 g - c 4 m u l t i s t a n d a r d s o u n d p r o c e s s o r f a m i l y e d i t i o n m a r c h 2 9 , 2 0 0 4 6 2 5 1 - 6 2 3 - 1 p d p r e l i m i n a r y d a t a s h e e t m i c r o n a s m i c r o n a s
2 march 29, 2004; 6251-623-1pd micronas contents page section title msp 44x8g-c4 preliminary data sheet 5 1. introduction 7 1.1. features of the msp 44x8g family 7 1.2. msp 44x8g version list 8 1.3. msp 44x8g versions and their application fields 10 2. functional description 11 2.1. architecture of the msp 44x8g family 11 2.2. msp 44x8g sound if processing 11 2.2.1. analog sound if input 11 2.2.2. demodulator: standards and features 12 2.2.3. preprocessing of demodulator signals 12 2.2.4. automatic sound select 12 2.2.5. manual mode 14 2.3. preprocessing for scart and i 2 s input signals 14 2.4. source selection and output channel matrix 14 2.4.1. mixing unit 14 2.5. audio baseband processing 14 2.5.1. automatic volume correction (avc) 15 2.5.2. main and aux outputs 15 2.5.3. quasi-peak detector 15 2.6. scart signal routing 15 2.6.1. scart dsp in and scart out select 15 2.6.2. stand-by mode 15 2.7. i 2 s bus interfaces 15 2.7.1. synchronous i 2 s-interface(s) 15 2.7.2. asynchronous i 2 s input interface 16 2.7.3. asynchronous i 2 s output interface 16 2.8. digital control i/o pins and status change indication 16 2.9. preemphasis 16 2.10. clock pll oscillator and crystal specifications 16 2.11. audio/video synchronization 17 3. control interface 17 3.1. device and subaddresses 17 3.1.1. internal hardware error handling 18 3.1.2. description of control register 18 3.1.3. protocol description 19 3.1.4. proposals for general msp 44x8g i 2 c telegrams 19 3.1.4.1. symbols 19 3.1.4.2. write telegrams 19 3.1.4.3. read telegrams 19 3.1.4.4. examples 19 3.2. start-up sequence: power-up and i 2 c-controlling 19 3.3. msp 44x8g programming interface 19 3.3.1. user registers overview 22 3.3.2. description of user registers 23 3.3.2.1. standard select register contents, continued page section title micronas march 29, 2004; 6251-623-1pd 3 preliminary data sheet msp 44x8g-c4 23 3.3.2.2. refresh of standard select register 23 3.3.2.3. standard result register 24 3.3.2.4. write registers on i 2 c subaddress 10 hex 27 3.3.2.5. read registers on i 2 c subaddress 11 hex 28 3.3.2.6. write registers on i 2 c subaddress 12 hex 36 3.3.2.7. read registers on i 2 c subaddress 13 hex 37 3.4. programming tips 37 3.5. examples of minimum initialization codes 37 3.5.1. b/g-fm (a2 or nicam) 37 3.5.2. btsc-stereo 37 3.5.3. btsc-sap with sap at main channel 38 3.5.4. fm-stereo radio 38 3.5.5. automatic standard detection 38 3.5.6. software flow for interrupt driven status check 40 4. specifications 40 4.1. outline dimensions 43 4.2. pin connections and short descriptions 46 4.3. pin descriptions 49 4.4. pin configurations 52 4.5. pin circuits 54 4.6. electrical characteristics 54 4.6.1. absolute maximum ratings 56 4.6.2. recommended operating conditions 56 4.6.2.1. general recommended operating conditions 57 4.6.2.2. analog input and output recommendations 58 4.6.2.3. recommendations for analog sound if input signal 59 4.6.2.4. crystal recommendations 60 4.6.3. characteristics 60 4.6.3.1. general characteristics 61 4.6.3.2. digital inputs, digital outputs 62 4.6.3.3. reset input and power-up 63 4.6.3.4. i 2 c-bus characteristics 64 4.6.3.5. i 2 s-bus characteristics 67 4.6.3.6. analog baseband inputs and outputs, agndc 69 4.6.3.7. sound if inputs 69 4.6.3.8. power supply rejection 70 4.6.3.9. analog performance 73 4.6.3.10. sound standard dependent characteristics 76 4.6.3.11. audio/video synchronization characteristics 4 march 29, 2004; 6251-623-1pd micronas contents, continued page section title msp 44x8g-c4 preliminary data sheet 77 5. appendix a: overview of tv-sound standards 77 5.1. nicam 728 78 5.2. a2-systems 79 5.3. btsc-sound system 79 5.4. japanese fm stereo system (eia-j) 80 5.5. fm satellite sound 80 5.6. fm-stereo radio 81 6. appendix b: manual mode 81 6.1. demodulator write and read registers for manual mode 82 6.2. dsp write and read registers for manual mode 82 6.3. manual mode: description of demodulator write registers 82 6.3.1. automatic switching between nicam and analog sound 82 6.3.1.1. function in automatic sound select mode 83 6.3.1.2. function in manual mode 84 6.3.2. a2 threshold 84 6.3.3. carrier-mute threshold 85 6.3.4. dco-registers 85 6.4. manual mode: description of demodulator read registers 86 6.4.1. nicam mode control/additional data bits register 86 6.4.2. additional data bits register 86 6.4.3. cib bits register 86 6.4.4. nicam error rate register 87 6.5. manual mode: description of dsp write registers 87 6.5.1. additional channel matrix modes 87 6.5.2. fm fixed deemphasis 87 6.5.3. fm adaptive deemphasis 87 6.5.4. nicam deemphasis 87 6.5.5. identification mode for a2 stereo systems 88 6.6. manual mode: description of dsp read registers 88 6.6.1. stereo detection register for a2 stereo systems 88 6.6.2. dc level register 88 6.7. demodulator source channels in manual mode 88 6.7.1. terrestrial sound standards 88 6.7.2. sat sound standards 90 7. appendix c: application information 90 7.1. exclusions of audio baseband features 90 7.2. phase relationship of analog outputs 91 7.3. application circuit 92 8. appendix d: msp 44x8g version history 92 9. data sheet history preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 5 multistandard sound processor family release note: revision bars indicate significant changes to the msp 44x8g data sheet, edition 16.06.03, 6251-516-1ds. the hardware and soft- ware description in this document is valid for the msp 44x8g version c4 and following versions. 1. introduction the msp 44x8g family of multistandard sound pro- cessors covers the demodulation and stereo decoding of all analog tv-standards worldwide, as well as the nicam digital sound standards and fm stereo radio. the full demodulation and decoding, starting with ana- log sound if signal in, down to processed analog or digital af (baseband audio) out, is performed on a sin- gle chip. fig. 1?1 on page 6 shows a simplified func- tional block diagram of the msp 44x8g. the msp 44x8g built-in stereo a/d converters offer a s/n ratio of 95 dba typ. the double stereo d/a con- verters with analog volume and 0.125 db steps make use of the micronas unique multibit delta-sigma tech- nology, offering a dynamic range of 95 dba typically. the dsp processing is performed at a 48 khz sample rate, maintaining the full audio bandwidth of 20 khz in all msp 44x8g signal paths. the msp 44x8g has been designed for the usage in dvd/hdd-recorders, hybrid set-top boxes, and multi- media applications. it combines the function of a tv stereo decoder together with an audio i 2 s codec and dsp audio processing features. its asynchronous i 2 s interfaces allows the reception and transmission of dig- ital stereo signals with arbitrary sample rates from 6 to 49 khz. in addition, a sample rate of 96 khz is also supported at the asynchronous i 2 s input. the msp 44x8g offers the following automatic func- tions: ? asd (automatic standard detection) detects the actual broadcasted tv standard automatically. ? ass (automatic sound se lect) switches automati- cally (without any i 2 c action) between mono/stereo/ bilingual when the broadcast mode changes. this generation of sound processing ics includes ver- sions for processing the multichannel television sound (mts) signal conforming to the u.s. standard recom- mended by the broadcast television systems commit- tee (btsc). the dbx noise reduction, or alternatively, micronas noise reduction (mnr) is performed align- ment free. apart from all 2-carrier standards, other pro- cessed standards are the japanese fm-fm multiplex standard (eia-j) and the fm stereo radio standard. the msp 44x8g versions are pin and software com- patible to other msp fam ilies. standard selection requires only a single i 2 c transmission. the ics are produced in submicron cmos technology and are available in the following packages: pmqfp80-11, pmqfp64- 2, and psdip64-1. msp 44x8g-c4 preliminary data sheet 6 march 29, 2004; 6251-623-1pd micronas fig. 1?1: simplified functional block diagram of the msp 44x8g source select scart1 scart2 scart1 scart2 scart4 scart3 mono aux aux i 2 s sound processing main sound processing dac dac adc main dac dac adc i 2 s1 i 2 s2 sound if1 sound if2 channel channel i 2 s3 de- modulator dac prescale synchron. i 2 s prescale asychron. i 2 s pre- processing scart dsp input select scart output select i2s asychron. i 2 s4 preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 7 1.1. features of the msp 44x8g family 1.2. msp 44x8g version list feature 4408 4418 4428 4448 4458 4468 standard selection with single i 2 c transmission x x x x x x automatic standard detection of terrestrial tv standards x x x x x x automatic sound selection (mono/stereo/bili ngual), new registers modus, status x x x x x x two selectable sound if (sif) inputs x x x x x x automatic carrier mute function x x x x x x interrupt output programmable (indicating status change) x x x x x x main/aux channel with volume x x x x x x avc: automatic volume correction x x x x x x two channel mixer xxxxxx selectable preemphasis for aux channel x x x x x x four stereo scart (line) inputs, one mono input; two stereo scart outputs x x x x x x complete scart in/out switching matrix x x x x x x two synchronous 48 khz i 2 s inputs; one synchronous 48 khz i 2 s output x x x x x x asynchronous 6...49, 96 khz i 2 s input, asynchronous 6..49 khz i 2 s output x x x x x x audio/video synchronization x x x x x x all analog mono sound carriers including am-secam x x x x x x korean fm-stereo a2 standard x x x x x all analog fm-stereo a2 and satellite standards x x x simultaneous demodulation of (very) high-deviation fm-mono and nicam x x adaptive deemphasis for satellite (wegener-panda, acc. to astra specification) x x x x all nicam standards xx demodulation of the btsc multiplex signal and the sap channel x x x alignment free digital dbx noise reduction for btsc stereo and sap x x alignment free digital micronas noise re duction (mnr) for btsc stereo and sap x btsc stereo and eia-j separation si gnificantly better than spec. x x x sap and stereo detection for btsc system x x x alignment-free japanese standard eia-j x x x demodulation of the fm-radio multiplex signal x x x version status description msp 4408g not confirmed fm stereo (a2) version msp 4418g available nicam and fm stereo (a2) version msp 4428g available ntsc version (a2 korea, btsc with micronas noise reduction (mnr), and japanese eia-j system) msp 4448g available ntsc version (a2 korea, btsc wi th dbx noise reduction, and japanese eia-j system) msp 4458g available global version (all sound standards) msp 4468g not confirmed global mono version (all sound standards) msp 44x8g-c4 preliminary data sheet 8 march 29, 2004; 6251-623-1pd micronas 1.3. msp 44x8g versions an d their application fields table 1?1 provides an overview of tv sound standards that can be processed by the msp 44x8g family. in addition, the msp 44x8g is able to handle the fm- radio standard. with the msp 44x8g, a dvd/hdd- recorder or multimedia rece iver covering all tv sound standards together with fm-radio sound can be built. table 1?1: tv stereo sound standards covered by the msp 44x8g family (details see appendix a) msp version system position of sound carrier / mhz sound modulation color system broadcast e.g. in: 4408 4418 4458 b/g 5.5/5.7421875 fm-stereo (a2) pal germany 5.5/5.85 fm-mono/nicam pal scandinavia, spain l 6.5/5.85 am-mono/nicam secam-l france i 6.0/6.552 fm-mono/nicam pal uk, hong kong d/k 6.5/5.85 fm-mono/nicam pal china, hungary 4408 6.5/6.2578125 fm-stereo (a2, d/k1) secam-east slovak. rep. 6.5/6.7421875 fm-stereo (a2, d/ k2) pal currently no broadcast 6.5/5.7421875 fm-stereo (a2, d/k3) secam-east poland satellite 6.5 7.02/7.2 7.38/7.56 etc. fm-mono fm-stereo pal europe sat. 4428/48 m 4.5/4.724212 fm-stereo (a2) ntsc korea 4.5 fm-fm (eia-j) ntsc japan 4.5 btsc-stereo + sap ntsc usa fm-radio 10.7 fm-stereo radio usa, europe 4468 all standards as above but mono demodulation only preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 9 fig. 1?2: typical msp 44x8g application scart outputs 32 40 mh z 4 .5 9 mh z main 2 2 scart2 scart1 msp 44x8g i 2 s1 2 2 2 2 scart1 scart2 scart3 scart4 1 mono saw filter tuner scart inputs i 2 s3 composite video (cvbs) channel aux channel/ fm-modulator aux channel drx3960a dsp i 2 s4 mpeg audio/video dvd/hdd vpx322xf audio/video sound if itu 656 d_ctr_i/o_0 if processing cvbs demodulator codec delayed tuner agc sync the scart inputs and outputs are equivalent to audio line inputs and outputs (left and right) with r in >10 kohm and r out <1 kohm and capable to accept/deliver 2 v rms. msp 44x8g-c4 preliminary data sheet 10 march 29, 2004; 6251-623-1pd micronas 2. functional description note: the scart inputs and outputs are equivalent to audio line inputs and outputs (left and right) with r in >10 kohm and r out <1 kohm and capable to accept/deliver 2 v rms. note: 1) avc location is programmable. i 2 c stereo or b stereo or a fm/am read register standard demodulator (incl. carrier mute) decoded ? nicam ? a2 ? am ? btsc ? eia-j ? sat ? fm-radio and sound detection standards: stereo or a/b automatic sound select standard selection (0e hex ) (10 hex ) deemphasis: 50/75 s, j17 dbx/mnr, panda1 deemphasis: j17 prescale fm/am nicam prescale (08 hex ) volume d a prescale prescale daca_l daca_r source select quasi-peak detector i 2 s channel matrix quasi-peak channel matrix main channel matrix aux channel matrix avc 1) volume i 2 s interface i 2 c read register i 2 s interface i 2 s interface sc1_in_l sc1_in_r sc2_in_l sc2_in_r sc3_in_l sc3_in_r sc4_in_l sc4_in_r mono_in prescale i2s_da_in1 i2s_da_in3 d a d a synchronization / interpolation (sync. 48 khz) (async. 6-49, 96 khz) a d dacm_l dacm_r d a preem- phasis a d agc ana_in1+ ana_in2+ i 2 s1 i 2 s3 scart scale mix2 scale mix1 scart dsp input select scart output select scart1_l/r scart2_l/r 0 1 3 4 5 7 15 2 i 2 s interface prescale i2s_da_in2 i 2 s2 6 (sync. 48 khz) mix1 channel matrix mix2 channel matrix (sync. 48 khz) i2s_cl i2s_ws i2s_cl3 i2s_ws3 (16 hex ) (12 hex ) (11 hex ) (0d hex ) (09 hex ) (0c hex ) (38 hex ) (39 hex ) (0a hex ) (41 hex ) (3a hex ) (3b hex ) (06 hex ) (07 hex ) (40 hex ) (00 hex ) (29 hex ) (34 hex ) beeper (14 hex ) avc 1) fig. 2?1: signal flow block diagram of the msp 44x8g (input and output names correspond to pin names). (13 hex ) (13 hex ) (29 hex ) sc2_out_l sc2_out_r sc1_out_l sc1_out_r scart2 channel matrix scart1 channel matrix volume volume (19 hex ) (1a hex ) i 2 s channel matrix i2s_da_out (0b hex ) i 2 s4 channel matrix i 2 s4 interface i2s_da_out4 (async. 6-49 khz) (46 hex ) i2s_cl4 i2s_ws4 synchronization / interpolation v-sync a/v sync preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 11 2.1. architecture of the msp 44x8g family fig. 2?1 shows a simplified block diagram of the ic. the block diagram contains all features of the msp 4458g. other members of the msp 44x8g family do not have the complete set of features: the demodu- lator handles only a subset of the standards presented in the demodulator block; nicam processing is only possible in the msp 4418g and msp 4458g. 2.2. msp 44x8g sound if processing 2.2.1. analog sound if input the input pins ana_in1+, ana_in2+, and ana_in ? offer the possibility to con nect two different sound if (sif) sources to the msp 44x8g. the preselected sound if signal is fed into an a/d-converter. an analog automatic gain circuit (agc) allows a wide range of input levels. the highpass filters, formed by the cou- pling capacitors at pins ana_in1+ and ana_in2+ (see section 7.3. ?application circuit? on page 91), are sufficient in most cases to suppress video compo- nents. some combinations of saw filters and sound if mixer ics, however, show large picture components on their outputs. in this case, further filtering is recom- mended. 2.2.2. demodulator: standards and features the msp 44x8g is able to demodulate all tv-sound standards worldwide including the digital nicam sys- tem. depending on the msp 44x8g version, the fol- lowing demodulation modes can be performed: a2 systems: detection and demodulation of two sep- arate fm carriers (fm1 and fm2), demodulation and evaluation of the identification signal of carrier fm2. nicam systems: (only possible in the msp 4418g and msp 4458g). demodulation and decoding of the nicam carrier, detection and demodulation of the ana- log fm or am carrier. for d/k-nicam, the fm carrier may have a maximum deviation of 384 khz. very high deviation fm-mono: detection and robust demodulation of one fm carrier with a maximum devi- ation of 540 khz. btsc-stereo: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detec- tion and evaluation of the pilot carrier, am demodula- tion of the (l ? r)-carrier and detection of the sap sub- carrier. processing of dbx noise reduction or micronas noise reduction (mnr). btsc-mono + sap: detection and fm demodulation of the aural carrier resulting in the mts/mpx signal. detection and evaluation of the pilot carrier, detection and fm demodulation of th e sap subcarrier. process- ing of dbx noise reduction or micronas noise reduc- tion (mnr). japan stereo: detection and fm demodulation of the aural carrier resulting in the mpx signal. demodulation and evaluation of the identification signal and fm demodulation of the (l ? r)-carrier. fm-satellite sound: demodulation of one or two fm carriers. processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the astra specification. fm-stereo-radio: detection and fm demodulation of the aural carrier resulting in the mpx signal. detection and evaluation of the pilot carrier and am demodula- tion of the (l ? r)-carrier. the demodulator blocks of all msp 44x8g versions have identical user interfaces. even completely differ- ent systems like the btsc and nicam systems are controlled the same way. standards are selected by means of msp standard codes. automatic processes handle standard detection and identification without controller interaction. the key features of the msp 44x8g demodulator blocks are standard selection: the controlling of the demodula- tor is minimized: all parameters, such as tuning fre- quencies or filter bandwidth, are adjusted automati- cally by transmitting one single value to the standard select register. for all standards, spe- cific msp standard codes are defined. automatic standard detection: if the tv sound stan- dard is unknown, the msp 44x8g can automatically detect the actual standard, switch to that standard, and respond the actual msp standard code. automatic carrier mute: to prevent noise effects or fm identification problems in the absence of an fm carrier, the msp 44x8g offers a configurable carrier mute feature, which is activated automatically if the tv sound standard is selected by means of the stan- dard select register. if no fm carrier is detected at one of the two msp demodulator channels, the corre- sponding demodulator output is muted. this is indi- cated in the status register. msp 44x8g-c4 preliminary data sheet 12 march 29, 2004; 6251-623-1pd micronas 2.2.3. preprocessing of demodulator signals the nicam signals must be processed by a deempha- sis filter and adjusted in level. the analog demodu- lated signals must be processed by a deemphasis fil- ter, adjusted in level, and dematrixed. the correct deemphasis filters are alread y selected by setting the standard in the standard select register. the level adjustment has to be done by means of the fm/ am and nicam prescale registers. the necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). it can be manually set by the fm matrix mode register or automatically by the automatic sound selection. 2.2.4. automatic sound select in the automatic sound select mode, the dematrix function is automatically selected based on the identifi- cation information in th e status register. no i 2 c inter- action is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). the demodulator supports the identification check by switching between mono compatible standards (stan- dards that have the same fm mono carrier) automati- cally and non-audible. if b/g-fm or b/g-nicam is selected, the msp will swit ch between these stan- dards. the same action is performed for the standards: d/k1-fm, d/k2-fm, d/k3-fm, and d/k-nicam. switching is only done in the absence of any stereo or bilingual identificati on. if identification is found, the msp keeps the detected standard. in case of high bit-error rates, the msp 44x8g auto- matically falls back from digital nicam sound to ana- log fm or am mono. table 2?1 summarizes all actions that take place when automatic sound select is switched on. to provide more flexibility, the automatic sound select block prepares four different source channels of demodulated sound (fig. 2?2). by choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loud- speaker, headphone, etc.). this is done by means of the source select registers. the following source channels of demodulated sound are defined: ? ?fm/am? channel: analog mono sound, stereo if available. in case of nicam, analog mono only (fm or am mono). ? ?stereo or a/b? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains both languages a (left) and b (right). ? ?stereo or a? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language a (on left and right). ? ?stereo or b? channel: analog or digital mono sound, stereo if available. in case of bilingual broad- cast, it contains language b (on left and right). fig. 2?2 and table 2?2 show the source channel assignment of the demodulated signals in case of automatic sound select mode for all sound standards. note: the analog primary input channel contains the signal of the mono fm/am carrier or the l+r signal of the mpx carrier. the secondary input channel con- tains the signal of the second fm carrier, the l ? r sig- nal of the mpx carrie r, or the sap signal. fig. 2?2: source channel assignment of demodulated signals in automatic sound select mode 2.2.5. manual mode fig. 2?3 shows the source channel assignment of demodulated signals in case of manual mode. if man- ual mode is required, more information can be found in section 6.7. ?demodulator source channels in manual mode? on page 88. fig. 2?3: source channel assignment of demodulated signals in manual mode source select fm/am stereo or a/b stereo or a stereo or b 0 1 3 4 primary fm/am prescale nicam prescale automatic sound select channel secondary channel nicam a nicam b ls ch. matrix output-ch. matrices must be set once to stereo. sc2 ch. matrix source select fm/am (stereo or a/b) 0 1 primary fm/am prescale nicam prescale fm-matrix channel secondary channel nicam a nicam b ls ch. matrix output-ch. matrices must be set according to the standard. nicam sc2 ch. matrix preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 13 table 2?1: performed actions of the automatic sound selection selected tv sound standard performed actions b/g-fm, d/k-fm, m-korea, and m-japan evaluation of the identification signal and automatic swit ching to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2?2. b/g-nicam, l-nicam, i-nicam, d/k-nicam evaluation of nicam-c-bits and automatic switchi ng to mono, stereo, or bilingual. preparing four demodulator source channels according to table 2?2. in case of bad or no nicam reception, the msp switches automatically to fm/am mono and switches back to nicam if possible. a hyster esis prevents periodical switching. b/g-fm, b/g-nicam or d/k1-fm, d/k2-fm, d/k3-fm, and d/k-nicam automatic searching for stereo/bilingual-identificat ion in case of mono transmission. automatic and non- audible changes between dual-fm and fm-nicam standa rds while listening to the basic fm-mono sound carrier. example: if starting with b/g-fm-stereo, there will be a periodical alternation to b/g-nicam in the absence of fm-stereo/bilingual or nicam-identification. once an identification is detected, the msp keeps the corresponding standard. btsc-stereo, fm radio evaluation of the pilot signal and autom atic switching to mono or stereo. preparing four demodulator source channels according to table 2?2. detection of the sap carrier. m-btsc-sap in the absence of sap, the msp switches to btsc-stereo if available. if sap is detected, the msp switches automatically to sap (see table 2?2). table 2?2: sound modes for the demodulator source channels with automatic sound select source channels in automatic sound select mode broadcasted sound standard selected msp standard code 3) broadcasted sound mode fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) m-korea b/g-fm d/k-fm m-japan 02 03, 08 1) 04, 05, 07, 0b 1) 30 mono mono mono mono mono stereo stereo stereo stereo stereo bilingual: languages a and b left = a right = b left = a right = b ab b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08, 03 2) 09 0a 0b, 04 2) , 05 2) 0c, 0d nicam not available or error rate too high analog mono analog mono analog mono analog mono mono analog mono nicam mono nicam mono nicam mono stereo analog mono nicam stereo nicam stereo nicam stereo bilingual: languages a and b analog mono left = nicam a right = nicam b nicam a nicam b btsc 20, 21 mono mono mono mono mono stereo stereo stereo stereo stereo 20 mono + sap mono mono mono mono stereo + sap stereo stereo stereo stereo 21 mono + sap left = mono right = sap left = mono right = sap mono sap stereo + sap left = mono right = sap left = mono right = sap mono sap fm radio 40 mono mono mono mono mono stereo stereo stereo stereo stereo 1) the automatic sound select process will automati cally switch to the mono compatible analog standard. 2) the automatic sound select process will automatica lly switch to the mono compatible digital standard. 3) the msp standard codes are defined in table 3?7 on page 22. msp 44x8g-c4 preliminary data sheet 14 march 29, 2004; 6251-623-1pd micronas 2.3. preprocessing for scart and i 2 s input signals the scart and i 2 s inputs need only be adjusted in level by means of the scart and i 2 s prescale regis- ters. 2.4. source selection and output channel matrix the source selector makes it possible to distribute all source signals (one of the demodulator source chan- nels, scart, or i 2 s input) to the desired output chan- nels (main, aux, etc.). all input and output signals can be processed simultaneously. each source channel is identified by a unique source address. for each output channel, the output channel matrix can be set to sound a, sound b, stereo, or mono. if automatic sound select is on, the output channel matrix can stay fixed to stereo (transparent) for demod- ulated signals. 2.4.1. mixing unit any source can be selected as the input for the two channels of the mixing unit. the mixer channel matri- ces and the scaling factors can be programmed sepa- rately for each channel. after adding up both channels, the signal is fed back and is available as source 15 (mix output) of the source selector. 2.5. audio baseband processing 2.5.1. automatic volume correction (avc) different sound sources (e.g. terrestrial channels, sat channels, or scart) fairly often do not have the same volume level. advertisements during movies usually have a higher volume level than the movie itself. this results in annoying volume changes. the avc solves this problem by equaliz ing the volume level. to prevent clipping, the avc?s gain decreases quickly in dynamic boost conditions . to suppress oscillation effects, the gain increases rather slowly for low level inputs. the decay time is programmable by means of the avc register (see page 31). for input signals ranging from ? 24 dbr to 0 dbr, the avc maintains a fixed output level of ? 18 dbr. fig. 2?4 shows the avc output level versus its input level. for prescale and volume regist ers set to 0 db, a level of 0 dbr corresponds to full scale input/output. this is ? scart input/output 0 dbr = 2.0 v rms ? loudspeaker output 0 dbr = 1.4 v rms fig. 2?4: simplified avc characteristics ? 30 ? 24 ? 18 ? 12 ? 6 input level ? 18 ? 24 output level 0 [dbr] [dbr] preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 15 2.5.2. main and aux outputs the main and aux output channels are adjustable in volume. a square wave beeper with adjustable fre- quency and volume can be added to them. 2.5.3. quasi-peak detector the quasi-peak readout register can be used to read out the quasi-peak level of any input source. the fea- ture is based on following filter time constants: ? attack time: 1.3 ms ? decay time: 37 ms 2.6. scart signal routing 2.6.1. scart dsp in and scart out select the scart dsp input select and scart output select blocks include full matrix switching facilities. to design a tv set with four pairs of scart-inputs and two pairs of scart-outputs, no external switching hardware is required. the switches are controlled by the acb user register (see page 33). 2.6.2. stand-by mode if the msp 44x8g is swit ched off by first pulling standbyq low and then (after >1 s delay) switching off dvsup and avsup, but keeping ahvsup ( ?stand-by?-mode ), the scart switches maintain their position and function. this allows the copying from scart-input to scart-output in the tv set?s stand-by mode. in case of power on or starting from stand-by (switch- ing on the dvsup and avsup, resetq going high 2 ms later), all internal registers except the acb regis- ter (see page 33) are reset to the default configuration (see table 3?5 on page 20). the reset position of the acb register becomes active after the first i 2 c trans- mission into the baseband processing part. by trans- mitting the acb register first, the reset state can be redefined. 2.7. i 2 s bus interfaces the msp 44x8g has two kinds of interfaces: synchro- nous master/slave input/output interfaces running on 48 khz and an asynchronous slave interface. the interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. all i 2 s options are set by means of the modus or i 2 s_config register. 2.7.1. synchronous i 2 s-interface(s) the synchronous i 2 s bus interface consists of the pins: ? i2s_da_in1, i2s_da_in2/3 (i2s_da_in2 in pmqfp80-11 package): i 2 s serial data input, 16, 18...32 bits per sample. ?i2s_da_out: i 2 s serial data output, 16, 18...32 bits per sample. ? i2s_cl: i 2 s serial clock. ?i2s_ws: i 2 s word strobe signal defines the left and right sample. if the msp 44x8g serves as the master on the i 2 s interface, the clock and word strobe lines are driven by the msp. in this mode, only 16, 32 bits per sample can be selected. in slave mode, these lines are input to the msp 44x8g and the msp clock is synchronized to 384 times the i2s_ws rate (48 khz). nicam operation is not possible in slave mode. an i 2 s timing diagram is shown in fig. 4?24 on page 65. 2.7.2. asynchronous i 2 s input interface the asynchronous i 2 s slave interface allows the reception of digital stereo signals with arbitrary sample rates from 6 to 49 khz. in addition, a sample rate of 96 khz is also supported at the asynchronous i 2 s input. the synchronization is performed by means of an adaptive sample rate converter. no oversampling clock is required. the following pins are used for the asynchronous i 2 s input interface: ? i2s_ws3 (serves only as input) ? i2s_cl3 (serves only as input) ? i2s_da_in2/3 (i2s_da_in3 in pmqfp80-11 pack- age). the interface accepts i 2 s-input streams with msb first and with sample widths of 16,18...32 bits. with left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the i 2 s-configuration regis- ter (see page 26). msp 44x8g-c4 preliminary data sheet 16 march 29, 2004; 6251-623-1pd micronas 2.7.3. asynchronous i 2 s output interface the asynchronous i 2 s master/slave interface allows the transmission of digital stereo signals with arbitrary sample rates from 6 to 49 khz. the synchronization is performed by means of an adaptive sample rate con- verter. in master mode, a programmable internal clock generator is used (see page 34). no oversampling clock is required. the following pins are used for the asynchronous i 2 s output interface: ?i2s_ws4 ? i2s_cl4 ?i2s_da_out4 the interface transmits i 2 s streams with msb first and with sample widths of 16 or 32 bits. with left/right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the i 2 s configuration2 regis- ter (see page 26). 2.8. digital control i/o pins and status change indication the static level of the digital input/output pins d_ctr_i/o_0/1 is switchable between high and low via the i 2 c-bus by means of the acb register (see page 33). this enable s the controlling of external hardware switches or other devices via i 2 c-bus. the digital input/output pins can be set to high imped- ance by means of the modus register (see page 25). in this mode, the pins can be used as input. the cur- rent state can be read out of the status register (see page 27). optionally, the pin d_ctr_i/o_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register status. this makes poll- ing unnecessary, i 2 c bus interactions are reduced to a minimum (see ?status register? on page 27 and ?modus register? on page 25). if audio/video synchronization is used, d_ctr_i/o_0 has to be programmed as input in the modus register and the field synchronization signal of the video color decoder (e.g. vpx 322xf pin vref_i) must be con- nected. 2.9. preemphasis when using the aux output for feeding an external modulator, a preemphasis can be applied to the right channel. the signal is scaled down by ? 3 db. an overmodula- tion protection is included in the algorithm which limits the output signal to 0 dbfs. due to the nature of a pre- emphasis, its gain at high frequencies exceeds 3 db. thus, even with 0 db input signals and prescaler / vol- ume set to 0 db, clipping can occur. there are three modes present: preemphasis off, 50 s, and 75 s. see table 3?11 on page 28 for the register settings. 2.10. clock pll oscillator and crystal specifications the msp 44x8g derives all internal system clocks from the 18.432 mhz oscilla tor. in nicam or in i 2 s- slave mode of the synchronous interface, the clock is phase-locked to the corresponding source. therefore, it is not possible to use nicam and i 2 s-slave mode of the synchronous interface at the same time. for proper performance, the msp clock oscillator requires a 18.432-mhz crystal. note that for the phase-locked modes (nicam, i 2 s-slave), crystals with tighter tolerance are required. please note also, that the asynchronous i 2 s3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances. 2.11. audio/video synchronization the i 2 s4 output interface can be used to synchronize audio and video data comp liant to standard aes11- 1997. if audio/video synchronization is active, d_ctr_i/o_0 has to be programmed as input in modus register and the fiel d synchronization signal of the video color decoder (e.g. vpx 322xf pin vref_i) must be connected. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 17 3. control interface 3.1. device and subaddresses the msp 44x8g is controlled via the i 2 c bus slave interface. the ic is selected by transmitting one of the msp 44x8g device addresses. in order to allow up to three msp ics to be connected to a single bus, an address select pin (adr_sel) has been implemented. with adr_sel pulled to high, low, or left open, the msp 44x8g responds to different device addresses. a device address pair is defined as a write address and a read address (see table 3?1). writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. reading is done by sending the write device address, followed by the subaddress byte and two address bytes. without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. refer to section 3.1.3. for the i 2 c bus protocol and to section 3.4. ?programming tips? on page 37 for pro- posals of msp 44x8g i 2 c telegrams. see table 3?2 for a list of available subaddresses. besides the possibility of hardware reset, the msp can also be reset by means of the reset bit in the con- trol register by the controller via i 2 c bus. due to the architecture of the msp 44x8g, the ic can- not react immediately to an i 2 c request. the typical response time is about 0.3 ms. if the msp cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line i2c_cl low to force the transmitter into a wait state. the i 2 c bus master must read back the clock line to detect when the msp is ready to receive the next i 2 c transmission. the positions within a transmission where this may happen are indicated by ?wait? in section section 3.1.3. the maximum wait period of the msp during normal operation mode is less than 1 ms. 3.1.1. internal hardware error handling in case of any hardware problems (e.g. interruption of the power supply of the msp), the msp?s wait period is extended to 1.8 ms. after this time period elapses, the msp releases data and clock lines. indication and solving the error status: to indicate the error status, the remaining acknowl- edge bits of the actual i 2 c-protocol will be left high. additionally, bit[14] of control is set to one. the msp can then be reset via the i 2 c bus by transmitting the reset condition to control. indication of reset: any reset, even caused by an unstable reset line etc., is indicated in bit[15] of control. a general timing diagram of the i 2 c bus is shown in fig. 4?23 on page 63. table 3?1: i 2 c bus device addresses adr_sel low (connected to dvss) high (connected to dvsup) left open mode write read write read write read msp device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex table 3?2: i 2 c bus subaddresses name binary value hex value mode function control 0000 0000 00 read/write write: software reset of msp (see table 3?3) read: hardware error status of msp wr_dem 0001 0000 10 write write address demodulator rd_dem 0001 0001 11 write read address demodulator wr_dsp 0001 0010 12 write write address dsp rd_dsp 0001 0011 13 write read address dsp msp 44x8g-c4 preliminary data sheet 18 march 29, 2004; 6251-623-1pd micronas 3.1.2. description of control register 3.1.3. protocol description write to dsp or demodulator read from dsp or demodulator write to control registers read from control register note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master ack = acknowledge-bit: low on i2c_da from slave (= msp, light gray) or master (= controller, dark gray) nak = not acknowledge-bit: high on i2c_da from master (dark gray) to indicate ?end of read? or from msp indicating internal error state wait = i 2 c-clock line is held low, while the msp is processing the i 2 c command. this waiting time is max. 1 ms table 3?3: control as a write register name subaddress bit[15] (msb) bits[14:0] control 00 hex 1 : reset 0 : normal 0 table 3?4: control as a read register name subaddress bit[15] (msb) bit [14] bit s[13:0] control 00 hex reset status after last reading of control: 0 : no reset occured 1 : reset occured internal hardware status: 0 : no error occured 1 : internal error occured not of interest reading of control will reset the bits [15,14] of control. after power-on, bit[15] of control will be set; it must be read once to be reset. swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack data-byte high ack data-byte low ack p swrite device address wait ack sub-addr ack addr-byte high ack addr-byte low ack s read device address wait ack data-byte- high ack data-byte low nak p swrite device address wait ack sub-addr ack data-byte high ack data-byte low ack p swrite device address wait ack 00hex ack s read device address wait ack data-byte- high ack data-byte low nak p preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 19 fig. 3?1: i 2 c bus protocol (msb first; data must be stable while clock is high) 3.1.4. proposals for general msp 44x8g i 2 c telegrams 3.1.4.1. symbols daw write device address (80 hex , 84 hex or 88 hex ) dar read device address (81 hex , 85 hex or 89 hex ) < start condition > stop condition aa address byte dd data byte 3.1.4.2. write telegrams msp 44x8g-c4 preliminary data sheet 20 march 29, 2004; 6251-623-1pd micronas table 3?5: list of msp 44x8g write registers write register address (hex) bits description and adjustable range reset see page i 2 c subaddress = 10 hex ; registers are not readable standard select 00 20 [15:0] initial programming of complete demodulator 00 00 24 modus 00 30 [15:0] demodulator, automatic and i 2 s options 00 00 25 i 2 s configuration 00 40 [15:0] configuration of i 2 s options 00 00 26 i 2 s async output config 00 50 [15:0] configuration of i 2 s4 options 00 00 26 i 2 c subaddress = 12 hex ; registers are all readable by using i 2 c subaddress = 13 hex volume main channel 00 00 [15:8] [ + 12 db ... ? 114 db, mute] mute 31 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin volume aux channel 00 06 [15:8] [ + 12 db ... ? 114 db, mute] mute 31 [7:5] [4:0] 1/8 db steps must be set to 0 000 bin 00000 bin volume scart1 output channel 00 07 [15:8] [ + 12 db ... ? 114 db, mute] mute 32 main source select 00 08 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 main channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 aux source select 00 09 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 aux channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 scart1 source select 00 0a [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 scart1 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 i 2 s source select 00 0b [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 i 2 s channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 quasi-peak detector source select 00 0c [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 quasi-peak detector matrix [7:0] [soun da, soundb, stereo, mono] sounda 30 prescale scart input 00 0d [15:8] [00 hex ... 7f hex ]00 hex 29 prescale fm/am 00 0e [15:8] [00 hex ... 7f hex ]00 hex 28 fm matrix [7:0] [no_mat, gstereo, kstereo] no_mat 29 prescale nicam 00 10 [15:8] [00 hex ... 7f hex ]00 hex 29 prescale i 2 s3 00 11 [15:8] [00 hex ... 7f hex ]10 hex 29 prescale i 2 s2 00 12 [15:8] [00 hex ... 7f hex ]10 hex 29 scart switches and d_ctr_i/o 00 13 [15:0] bits [15:0] 00 hex 33 beeper 00 14 [15:0] [00 hex ... 7f hex ]/[00 hex ... 7f hex ] 00/00 hex 34 prescale i 2 s1 00 16 [15:8] [00 hex ... 7f hex ]10 hex 29 avc: automatic volume correction 00 29 [15:8] [off, on, decay time] off 31 i2s4 output sample frequency 00 2a [15:0] [48khz .. 8khz] 00 hex 34 audio/video synchronization 00 2b [15:0] [on, default freq automatic mode, manual mode] 00 hex 35 aux preemphasis on right channel 00 34 [15:8] [off, 50 s, 75 s] off 31 mix1 source select 00 38 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 mix1 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 21 mix2 source select 00 39 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm/am 30 mix2 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 scale mix1 00 3a [15:8] [00 hex ... 7f hex ]00 hex 34 scale mix2 00 3b [15:8] [00 hex ... 7f hex ]00 hex 34 volume scart2 output channel 00 40 [15:8] [ + 12 db ... ? 114 db, mute] 00 hex 32 scart2 source select 00 41 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm 30 scart2 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 i2s4 source select 00 46 [15:8] [fm/am, nicam, scart, i 2 s1..3, mix output] fm 30 i2s4 channel matrix [7:0] [sounda, soundb, stereo, mono] sounda 30 table 3?6: list of msp 44x8g read registers read register address (hex) bits description and adjustable range see page i 2 c subaddress = 11 hex ; registers are not writable standard result 00 7e [15:0] result of automatic standard detection (see table 3?8) 27 status 02 00 [15:0] monitoring of settings e.g. stereo, mono, mute, d_ctr_i/o etc. . 27 i 2 c subaddress = 13 hex ; registers are not writable quasi peak readout left 00 19 [15:0] [00 hex ... 7fff hex ]16 bit two?s complement 36 quasi peak readout right 00 1a [15:0] [00 hex ... 7fff hex ]16 bit two?s complement 36 msp hardware version code 00 1e [15:8] [00 hex ... ff hex ]36 msp major revision code [7:0] [00 hex ... ff hex ]36 msp product code 00 1f [15:8] [00 hex ... ff hex ]36 msp rom version code [7:0] [00 hex ... ff hex ]36 table 3?5: list of msp 44x8g write registers, continued write register address (hex) bits description and adjustable range reset see page msp 44x8g-c4 preliminary data sheet 22 march 29, 2004; 6251-623-1pd micronas 3.3.2. description of user registers table 3?7: standard codes for standard select register msp standard code (data in hex) tv sound standard sound carrier frequencies in mhz msp 44x8g version automatic standard detection 00 01 starts automatic standard detection and sets to detected standard all standard selection 00 02 m-dual fm-stereo 4.5/4.724212 4408, -18, -48, -58 00 03 b/g-dual fm-stereo 1) 5.5/5.7421875 4408, -18, -58 00 04 d/k1-dual fm-stereo 2) 6.5/6.2578125 00 05 d/k2-dual fm-stereo 2) 6.5/6.7421875 00 06 d/k-fm-mono with hdev3 3) , not detectable by automatic standard detection, hdev3 3) sat-mono (i.e. eutelsat, see table 6?12) 6.5 00 07 d/k3-dual fm-stereo 6.5/5.7421875 4408, -18, -58 00 08 b/g-nicam-fm 1) 5.5/5.85 4418, -58 00 09 l-nicam-am 6.5/5.85 00 0a i-nicam-fm 6.0/6.552 00 0b d/k-nicam-fm 2) 6.5/5.85 00 0c d/k-nicam-fm with hdev2 4) , not detectable by automatic standard detection, for china 6.5/5.85 00 0d d/k-nicam-fm with hdev3 3) , not detectable by automatic standard detection, for china 6.5/5.85 4418, -58 00 20 btsc-stereo 4.5 4428, -48, -58 00 21 btsc-mono + sap 00 30 eia-j japan stereo 4.5 4428, -48, -58 00 40 fm-stereo radio with 75 s deemphasis 10.7 4428, -48, -58 00 50 sat-mono (see table 6?12) 6.5 4408, -18, -58 00 51 sat-stereo (see table 6?12 ) 7.02/7.20 4408, -18, -58 1) in case of automatic sound select, the b/g-codes 3 hex and 8 hex are equivalent. 2) in case of automatic sound select, the d/k-codes 4 hex , 5 hex , 7 hex and b hex are equivalent. 3) hdev3: max. fm deviation must not exceed 540 khz 4) hdev2: max. fm deviation must not exceed 360 khz preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 23 3.3.2.1. standard select register the tv sound standard of the msp 44x8g demodula- tor is determined by the standard select register. there are two ways to use the standard select register: ? setting up the demodulator for a tv sound standard by sending the corresponding standard code with a single i 2 c bus transmission. ? starting the automatic standard detection for ter- restrial tv standards. this is the most comfortable way to set up the demodulator. within 0.5 s, the detection and setup of the actual tv sound standard is performed. the detected standard can be read out of the standard result register by the con- trol processor. this feature is recommended for the primary setup of a tv set. outputs should be muted during automatic standard detection. the standard codes are listed in table 3?7. selecting a tv sound standard via the standard select register initializ es the demodulator. this includes: agc-settings and carrier mute, tuning fre- quencies, fir-filter settings, demodulation mode (fm, am, nicam), deemphasis and identification mode. tv stereo sound standards that are unavailable for a specific msp version are processed in analog mono sound of the standard. in t hat case, stereo or bilingual processing will not be possible. for a complete setup of the tv sound processing from analog if input to the source selection, the transmis- sions as shown in section 3.5. on page 37 are neces- sary. there is a manual mode. 3.3.2.2. refresh of st andard select register a general refresh of the standard select register is not allowed. however, the following method enables watching the msp 44x8g ?alive? status and detection of accidental resets (only versions b6 and later): ? after power-on, bit[15] of control will be set; it must be read once to enable the reset-detection feature. ? reading of the control register and checking the reset indicator bit[15] . ? if bit[15] is ?0?, any refresh of the standard select register is not allowed. ? if bit[15] is ?1?, indicating a reset, a refresh of the standard select register and all other mspg registers is required. 3.3.2.3. standard result register if automatic standard detect ion is selected in the standard select register, status and result of the automatic standard detection process can be read out of the standard result register. the possible results are based on the mentioned standard code and are listed in table 3?8. in cases where no sound standard has been detected (no standard present, too much noise, strong interfer- ers, etc.) the standard result register contains 00 00 hex . in that case, the controller has to start further actions (for example set the standard according to a preference list or by manual input). as long as the standard result register contains a value greater than 07 ff hex , the automatic standard detection is still active. during this period, the modus and standard select register must not be written. the status register will be updated when the auto- matic standard detection has finished. if a present sound standard is unavailable for a specific msp-version, it detects and switches to the analog mono sound of this standard. example: the msp 4448g will detect a b/g-nicam signal as standard 3 and will switch to the analog fm-mono sound. msp 44x8g-c4 preliminary data sheet 24 march 29, 2004; 6251-623-1pd micronas 3.3.2.4. write registers on i 2 c subaddress 10 hex table 3?8: results of the automatic standard detection broadcasted sound standard standard result register read 007e hex automatic standard detection could not find a sound standard 0000 hex b/g-fm 0003 hex b/g-nicam 0008 hex i000a hex fm-radio 0040 hex m-korea m-japan m-btsc 0002 hex (if modus[14,13]=00) 0020 hex (if modus[14,13]=01) 0030 hex (if modus[14,13]=10) l-am d/k1 d/k2 d/k3 0009 hex (if modus[12]=0) 0004 hex (if modus[12]=1) l-nicam d/k-nicam 0009 hex (if modus[12]=0) 000b hex (if modus[12]=1) automatic standard detection still active >07ff hex table 3?9: write registers on i 2 c subaddress 10 hex register address function name standard selection 00 20 hex standard selection register defines tv sound or fm-radio standard bit[15:0] 00 01 hex start automatic standard detection 00 02 hex standard codes (see table 3?7) ... 00 60 hex standard_sel preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 25 modus 00 30 hex modus register preference in automatic standard detection: bit[15] 0 reserved, must be 0 bit[14:13] detected 4.5 mhz carrier is interpreted as: 1) 0 standard m (korea) 1 standard m (btsc) 2 standard m (japan) 3 chroma carrier (m/n standards are ignored) bit[12] detected 6.5 mhz carrier is interpreted as: 1) 0 standard l (secam) 1 standard d/k1, d/k2, d/k3, or d/k nicam general msp 44x8g options bit[11:9] 0 reserved, must be 0 bit[8] 0/1 ana_in1+/ana_in2+; select analog sound if input pin bit[7] 0/1 active/tristate state of audio clock output pin aud_cl_out bit[6] word strobe alignment (synchronous i 2 s) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[5] 0/1 master/slave mode of i 2 s interface (must be set to 0 (= master) in case of nicam mode) bit[4] 0/1 active/tristate state of i 2 s output pins bit[3] state of digital output pins d_ctr_i/o_0 and _1 0 active: d_ctr_i/o_0 and _1 are output pins (can be set by means of the acb register. see also: modus[1]) 1 tristate: d_ctr_i/o_0 and _1 are input pins (level can be read out of status[4,3]) tristate is needed for a/v synchronization mode. bit[2] 0 reserved, must be 0 bit[1] 0/1 disable/enable status change indication by means of the digital i/o pin d_ctr_i/o_1 necessary condition: modus[3] = 0 (active) bit[0] 0/1 off/on: automatic sound select modus 1) valid at the next start of automatic standard detection. table 3?9: write registers on i 2 c subaddress 10 hex , continued register address function name msp 44x8g-c4 preliminary data sheet 26 march 29, 2004; 6251-623-1pd micronas 0040 hex i 2 s configuration register (not mentioned bit combinations must not be used) bit[15:12] 0 undefined, must be set to 0 bit[11] i 2 s data alignment (i 2 s_3) 0 left aligned 1 right aligned bit[10] word strobe polarity (i 2 s_3) 0 1 = right, 0 = left 1 0 = right, 1 = left bit[9] word strobe alignment (asynchronous i 2 s_3) 0 ws changes at data word boundary 1 ws changes one clock cycle in advance bit[8:2] 0 undefined, must be set to 0 bit[1:0] i2s_cl frequency and i 2 s_da_out sample length 00 2 * 16 bit (1.536 mhz clk) 01 2 * 32 bit (3.072 mhz clk) 1x undefined, must not be used i2s_config 0050 hex i 2 s configuration2 register bit[15:6] 0 undefined, must be set to 0 bit[5] pad driver strength (i2s_4) 0weak 1strong bit[4] enable/disable i2s out (i2s_4) 0 asyn-i2s-out off 1 asyn-i2s-out on bit[3] master / slave mode of i2s out (i2s_4) 0master 1slave bit[2] i2s out word strobe polarity (i2s_4) 0 1 = right, 0 = left (l = low, r = high) 1 0 = right, 1 = left (l = high, r = low) bit[1] i2s out word strobe alignment (i2s_4) 0 wordstrobe changes at data word boundary 1 wordstrobe changes one clock cycle in advance bit[0] i2s_cl4 frequency and i 2 s_da_out4 sample length 0 32-bit/sample 1 16-bit/sample i2s_config2 i2s4_strength i2s4_mode i2s4_slave i2s4_ws_pol i2s4_ws_mode i2s4_wlen table 3?9: write registers on i 2 c subaddress 10 hex , continued register address function name preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 27 3.3.2.5. read registers on i 2 c subaddress 11 hex table 3?10: read registers on i 2 c subaddress 11 hex register address function name 00 7e hex standard result register readback of the detected tv sound or fm-radio standard bit[15:0] 00 00 hex automatic standard detection could not find a sound standard 00 02 hex msp standard codes (see table on page 26) ... 00 40 hex >07 ff hex automatic standard detection still active standard_res 02 00 hex status register contains all user relevant internal information about the status of the msp bit[15:10] undefined bit[8] 0/1 ?1? indicates bilingu al sound mode or sap present (internally evaluated from received analog or digital identification signals) bit[7] 0/1 ?1? indicates independent mono sound (only for nicam) bit[6] 0/1 mono/stereo indication bit[5,9] 00 analog sound standard (fm or am) active 01 this pattern will not occur 10 digital sound (nicam) available 11 bad reception condition of digital sound (nicam) due to: a. high error rate b. unimplemented sound code c. data transmission only bit[4] 0/1 low/high level of digital i/o pin d_ctr_i/o_1 bit[3] 0/1 low/high level of digital i/o pin d_ctr_i/o_0 in a/v synchronization mode, this information is not available. bit[2] 0 detected secondary carrier (2nd a2 or sap carrier) 1 no secondary carrier detected bit[1] 0 detected primary carrier (mono or mpx carrier) 1 no primary carrier detected bit[0] undefined if status change indication is activated by means of modus[1]: each change in the status register sets the digital i/o pin d_ctr_i/o_1 to high level. reading the status r egister resets d_ctr_i/o_1. status msp 44x8g-c4 preliminary data sheet 28 march 29, 2004; 6251-623-1pd micronas 3.3.2.6. write registers on i 2 c subaddress 12 hex table 3?11: write registers on i 2 c subaddress 12 hex register address function name preprocessing 00 0e hex fm/am prescale bit[15:8] 00 hex defines the input prescale gain for the demodulated ... fm or am signal 7f hex 00 hex off (reset condition) for all fm modes except satellite fm a nd am-mode, the combinations of pres- cale value and fm deviation listed below le ad to internal full scale with 1 khz test signal and 50 s emphasis. fm mode bit[15:8] 7f hex 28 khz fm deviation 48 hex 50 khz fm deviation 30 hex 75 khz fm deviation 24 hex 100 khz fm deviation 18 hex 150 khz fm deviation 13 hex 180 khz fm deviation (limit) fm high deviation mode (hdev2, msp standard code = c hex ) bit[15:8] 30 hex 150 khz fm deviation 14 hex 360 khz fm deviation (limit) fm very high deviation mode (hdev3, msp standard code = 6) bit[15:8] 20 hex 450 khz fm deviation 1a hex 540 khz fm deviation (limit) satellite fm with ad aptive deemphasis bit[15:8] 10 hex recommendation am mode (msp standard code = 9) bit[15:8] 7c hex recommendation for sif input levels from 0.1 v pp to 0.8 v pp (due to the agc switched on, the am-output level remains stable and independent of the actual sif-level in the men- tioned input range) pre_fm preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 29 (continued) 00 0e hex fm matrix modes defines the dematrix function for the demodulated fm signal bit[7:0] 00 hex no matrix (used for bilingual and unmatrixed stereo sound) 01 hex german stereo (standard b/g) 02 hex korean stereo (also used for btsc, eia-j, and fm radio) 03 hex sound a mono (left and right channel contain the mono sound of the fm/am mono carrier) 04 hex sound b mono (i.e. sap) in case of automatic sound select = on , the fm matrix mode is set automati- cally. writing to the fm/am prescale register (00 0e hex high part) is still allowed. in order not to disturb the automatic process, the low part of any i 2 c transmis- sion to this register is ignored. therefore, any fm-matrix readback values may differ from data written previously. in case of automatic sound select = off , the fm matrix mode must be set as shown in table 6?11 of appendix b. to enable a forced mono mode set a2 threshold as described in section 6.3.2. on page 84 fm_matrix 00 10 hex nicam prescale defines the input prescale value for the digital nicam signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 20 hex 0 db gain 5a hex 9 db gain (recommendation) 7f hex + 12 db gain (maximum gain) pre_nicam 00 16 hex 00 12 hex 00 11 hex i2s1 prescale i2s2 prescale i2s3 prescale defines the input prescale value for digital i 2 s input signals bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 10 hex 0 db gain (recommendation) 7f hex + 18 db gain (maximum gain) pre_i2s1 pre_i2s2 pre_i2s3 00 0d hex scart input prescale defines the input prescale value for the analog scart input signal bit[15:8] 00 hex ... 7f hex prescale gain examples: 00 hex off 19 hex 0 db gain (2 v rms input leads to digital full scale) 7f hex + 14 db gain (400 mv rms input leads to digital full scale) pre_scart table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 44x8g-c4 preliminary data sheet 30 march 29, 2004; 6251-623-1pd micronas source select and output channel matrix 00 08 hex 00 09 hex 00 0a hex 00 41 hex 00 0b hex 00 0c hex 00 38 hex 00 39 hex 00 46 hex source for: main output aux output scart1 da output scart2 da output i 2 s output quasi-peak detector mix1 input mix2 input i2s4 async output bit[15:8] 00 hex ?fm/am?: demodulated fm or am mono signal 01 hex ?stereo or a/b?: demodulator stereo or a/b signal 03 hex ?stereo or a?: demodulator stereo sound or language a (only defined for automatic sound select) 04 hex ?stereo or b?: demodulator stereo sound or language b (only defined for automatic sound select) 02 hex scart input 05 hex i 2 s1 input 06 hex i 2 s2 input 07 hex i 2 s3 input 0f hex mix output for demodulator sources, see table 2?2. src_main src_aux src_scart1 src_scart2 src_i2s src_qpeak src_mix1 src_mix2 src_i2s4 00 08 hex 00 09 hex 00 0a hex 00 41 hex 00 0b hex 00 0c hex 00 38 hex 00 39 hex 00 46 hex matrix mode for: main output aux output scart1 da output scart2 da output i 2 s output quasi-peak detector mix1 input mix2 input i2s4 async output bit[7:0] 00 hex sound a mono (or left mono) 10 hex sound b mono (or right mono) 20 hex stereo (transparent mode) 30 hex mono (sum of left and right inputs divided by 2) more modes are listed in section 6.5.1. in automatic sound select mode, the demodulator source channels are set according to table 2?2. therefore, the matrix modes of the corresponding output channels should be set to ?stereo? (transparent). mat_main mat_aux mat_scart1 mat_scart2 mat_i2s mat_qpeak mat_mix1 mat_mix2 mat_i2s4 table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 31 main and aux processing 00 00 hex 00 06 hex volume main volume aux bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex ? 1db ... 02 hex ? 113 db 01 hex ? 114 db 00 hex mute (reset condition) ff hex fast mute (needs about 75 ms until the signal is com- pletely ramped down) bit[7:5] higher resolution volume table 0 + 0db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] not used must be set to 0 with large scale input signals, positive volu me settings may lead to signal clipping. the msp 44x8g main and aux volume function is divided into a digital and an analog section. with fast mute, volume is reduced to mute position by digital vol- ume only. analog volume is not changed. this reduces any audible dc plops. to turn volume on again, the volume step that has been used before fast mute was activated must be transmitted. vol_main vol_aux 00 29 hex automatic volume correction (avc) loudspeaker channel bit[15] 00 hex avc off (and reset internal variables) 01 hex avc on bit[14] 00 hex avc is located in main path 01 hex avc is located in mixer path bit[11:8] 08 hex 8 sec decay time 04 hex 4 sec decay time 02 hex 2 sec decay time 01 hex 20 ms decay time (should be used for approx. 100 ms after channel change) avc 00 34 hex preemphasis aux channel bit[15:8] 00 hex preemphasis off 7f hex preemphasis 50 s ( ? 3 db scaling) ff hex preemphasis 75 s ( ? 3 db scaling) preemp_aux table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 44x8g-c4 preliminary data sheet 32 march 29, 2004; 6251-623-1pd micronas scart output channel 00 07 hex 00 40 hex volume scart1 output channel volume scart2 output channel bit[15:8] volume table with 1 db step size 7f hex + 12 db (maximum volume) 7e hex + 11 db ... 74 hex + 1db 73 hex 0db 72 hex ? 1db ... 02 hex ? 113 db 01 hex ? 114 db 00 hex mute (reset condition) bit[7:5] higher resolution volume table 0 + 0 db 1 + 0.125 db increase in addition to the volume table ... 7 + 0.875 db increase in addition to the volume table bit[4:0] 01 hex this must be 01 hex vol_scart1 vol_scart2 table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 33 scart switches and digital i/o pins 00 13 hex acb register defines the level of the digital output pins and the position of the scart switches bit[15] 0/1 low/high of digital output pin d_ctr_i/o_1 (modus[3]=0) bit[14] 0/1 low/high of digital output pin d_ctr_i/o_0 (modus[3]=0) bit[13:5] scart dsp input select xxxx00 xx0 scart1 to dsp input (reset position) xxxx01 xx0 mono to dsp input (set sound a mono in the channel matrix mode for the corresponding output channels) xxxx10 xx0 scart2 to dsp input xxxx11 xx0 scart3 to dsp input xxxx00 xx1 scart4 to dsp input xxxx11 xx1 mute dsp input bit[13:5] scart1 output select xx00xx x0x scart3 input to scart1 output (reset position) xx01xx x0x scart2 input to scart1 output xx10xx x0x mono input to scart1 output xx11xx x0x scart1 da to scart1 output xx00xx x1x scart2 da to scart1 output xx01xx x1x scart1 input to scart1 output xx10xx x1x scart4 input to scart1 output xx11xx x1x mute scart1 output bit[13:5] scart2 output select 00xxxx 0xx scart1 da to scart2 output (reset position) 01xxxx 0xx scart1 input to scart2 output 10xxxx 0xx mono input to scart2 output 00xxxx 1xx scart2 da to scart2 output 01xxxx 1xx scart2 input to scart2 output 10xxxx 1xx scart3 input to scart2 output 11xxxx 1xx scart4 input to scart2 output 11xxxx 0xx mute scart2 output bit[4:0] must be zero the reset position becomes active at the time of the first write transmission on the control bus to the audio processing part. by writing to the acb register first, the reset state c an be redefined. acb_reg table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 44x8g-c4 preliminary data sheet 34 march 29, 2004; 6251-623-1pd micronas mixing unit 00 3a hex 00 3b hex mix1 scale mix2 scale defines the input scale value for the digital mixing unit bit[15:8] 00 hex off 20 hex 50% ( ? 6db gain) 40 hex 100% (0 db gain) 7f hex 200% (+6 db gain = maximum gain) note: if the sum of both mixing inputs exceeds 100%, clipping may occur in the successive processing. vol_mix1 vol_mix2 beeper 00 14 hex beeper volume and frequency bit[15:8] beeper volume 00 hex off 7f hex maximum volume bit[7:0] beeper frequency 01 hex 16 hz (lowest) 40 hex 1khz ff hex 4khz beeper i2s async output interface 00 2a hex i2s4 output sample frequency programs the i2s4 output sample frequency in master mode. in slave mode, this register has no effect. bit[15:0] fs out [khz] 32 bit/sample 16 bit/sample 48 18 00 hex 30 00 hex 44.1 1a 1f hex 34 3f hex 32 24 00 hex 48 00 hex 24 30 00 hex 60 00 hex 22.05 34 3f hex 68 7d hex 16 48 00 hex 90 00 hex 12 60 00 hex c0 00 hex 11.025 68 7d hex d0 fb hex 8 90 00 hex ___ i2s4_out_fs table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 35 audio/video synchronization 00 2b hex audio/video synchronization controls the i 2 s4 output sample frequency according to the field synchronization frequency input at pin d_ctr_i/o_0 (e.g. of vpx 322xf, pin vref_i). to use the audio/video synchronization, d_ctr_i/o_0 must be set to tristate (modus[3]=1). audio/video synchronization is only su pported for the nominal i2s4 sample frequencies 48 khz, 44.1 khz, or 32 khz which has to be defined in the i2s4_out_fs register. i 2 s4 sample length i2s4_wlen must be set to 32 bit per sample. audio/video synchronization is compliant to standard aes11-1997 and supports the field frequencies pal/secam (50 hz), ntsc (59.94 hz), and monochrome (60 hz). it is recommended to disable audio/ video synchronization during a channel switch and enable it when the v-sync signal is stable. bit[15] enable audio/video synchronization 0off 1on bit[14] default field frequency for automatic video standard detection (bit[2:0] = 0) 0 monochrome (field frequency = 60 hz) 1 ntsc (field frequency = 59.94 hz) bit[13:3] reserved, set to 0 bit[2:0] video standard selection 0 hex automatic video standard detection 1 hex pal / secam (field frequency = 50 hz) 2 hex ntsc (field frequency = 59.94 hz) 4 hex monochrome (field frequency = 60 hz) if no video standard is selected (bit[2:0] = 0), the automatic video standard detection is active. in this mode, field frequency is mea- sured and the video standard is automatically switched to pal / secam (field frequency = 50 hz) or to the frequency defined with bit[14] (monochrome or ntsc). attention: mode changes only have effect if a/v synchronization is switched off and on again. av_sync av_on av_autofreq av_std_sel status2 00 7b hex status2 register bit[14] status of audio/video synchronization 0 no a/v synchronization. possible reasons: check if frequency i2s4_out_fs is set to 48 khz, 44.1 khz, or 32 khz check if a/v synchronization is switched on. check v-sync signal at pin d_ctr_i/o_0: is the v-sync signal stable? is the v-sync frequency in range of 5%? 1 a/v synchronization is active. status2 av_active table 3?11: write registers on i 2 c subaddress 12 hex , continued register address function name msp 44x8g-c4 preliminary data sheet 36 march 29, 2004; 6251-623-1pd micronas 3.3.2.7. read registers on i 2 c subaddress 13 hex table 3?12: read registers on i 2 c subaddress 13 hex register address function name quasi-peak detector readout 00 19 hex 00 1a hex quasi-peak detector readout left quasi-peak detector readout right bit[15:0] 0 hex ... 7fff hex values are 16 bit two?s complement (only positive). a value of 4000 hex corre- sponds to internal full scale. qpeak_l qpeak_r msp 44x8g version readout registers 001e hex msp hardware version code bit[15:8] 03 hex msp 44x8g- c 4 a change in the hardware version code defines hardware optimizations that may have influence on the chip?s behavior. the readout of this register is identi- cal to the hardware version code in the chip?s imprint. msp_hard msp family code bit[7:4] 1 hex msp 44 x8g-c4 msp_family msp major revision code bit[3:0] 7 hex msp 44x8 g -c4 msp_revision 001f hex msp product code bit[15:8] 08 hex msp 44 08 g-c4 12 hex msp 44 18 g-c4 1c hex msp 44 28 g-c4 30 hex msp 44 48 g-c4 3a hex msp 44 58 g-c4 by means of the msp-product code, the control processor is able to decide which tv sound standards have to be considered. msp_product msp rom version code bit[7:0] 44 hex msp 44x8g-c 4 a change in the rom version code defines internal software optimizations, that may have influence on the chip?s behavior, e.g. new features may have been included. while a software c hange is intended to cr eate no compatibility prob- lems, customers that want to use the new functions can identify new msp 44x8g versions according to this number. msp_rom preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 37 3.4. programming tips this section describes the preferred method for initial- izing the msp 44x8g. the init ialization is grouped into four sections: ? scart signal path (analog signal path) ? demodulator ? scart and i2s inputs ? output channels see fig. 2?1 on page 10 for a complete signal flow. scart signal path 1. select analog input for the scart baseband pro- cessing (scart dsp input select) by means of the acb register. 2. select the source for each analog scart output (scart output select) by means of the acb regis- ter. demodulator for a complete setup of the sound processing from analog if input to the source selection, the following steps must be performed: 1. set modus register to the preferred mode and sound if input. 2. write standard select register. 3. choose preferred prescale (fm and nicam) values. 4. if automatic sound select is not active: choose fm matrix repeatedly according to the sound mode indicated in the status register. scart and i 2 s inputs 1. select preferred prescale for scart. 2. select preferred prescale for i 2 s inputs (set to 0 db after reset). output channels 1. select the source channel and matrix for each out- put channel. 2. set audio baseband features (i.e. avc, 75 s pre- emphasis) 3. select volume for each output channel. 3.5. examples of minimum initialization codes initialization of the msp 44x8g according to these list- ings reproduces sound of the selected standard on the main output. all numbers are hexadecimal. the exam- ples have the following structure: 1. perform an i 2 c controlled reset of the ic. 2. write modus register (with automatic sound select). 3. set source selection for main channel (with matrix set to stereo). 4. set prescale (fm and/or nicam and dummy fm matrix). 5. write standard select register. 6. set volume main channel to 0 db. 3.5.1. b/g-fm (a2 or nicam) <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = mono/sounda <801200105a00> // nicam-prescale = 5a hex <801000200003> // standard select: a2 b/g or nicam b/g or <801000200008> <801200007300> // main volume 0 db 3.5.2. btsc-stereo <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200020> // standard select: btsc-stereo <801200007300> // main volume 0 db 3.5.3. btsc-sap with sap at main channel <80008000> // softreset <80000000> <801000302003> // modus-register: automatic = on <801200080420> // source sel. = (st or b) & ch. matr. = st <8012000e2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200021> // standard select: btsc-sap <801200007300> // main volume 0 db msp 44x8g-c4 preliminary data sheet 38 march 29, 2004; 6251-623-1pd micronas 3.5.4. fm-stereo radio <80 00 80 00> // softreset <80 00 00 00> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <80 12 000e 2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801000200040> // standard select: fm-stereo-radio <801200007300> // main volume 0 db 3.5.5. automatic standard detection a detailed software flow diagram is shown in fig. 3?2 on page 39. <80 00 80 00> // softreset <80 00 00 00> <801000302003> // modus-register: automatic = on <801200080320> // source sel. = (st or a) & ch. matr. = st <80 12 000e 2403> // fm/am-prescale = 24 hex , fm-matrix = sound a mono <801200105a00> // nicam-prescale = 5a hex <801000200001> // standard select: automatic standard detection // wait till standard result contains a value 07ff // if standard result contains 0000 // do some error handling // else <801200007300> // main volume 0 db 3.5.6. software flow for interrupt driven status check a detailed software flow diagram is shown in fig. 3?2 on page 39. if the d_ctr_i/o_1 pin of the msp 44x8g is con- nected to an interrupt input pin of the controller, the fol- lowing interrupt handler can be applied to be automati- cally called with each status change of the msp 44x8g. the interrupt handler may adjust the dis- play according to the new status information. interrupt handler: <80 11 02 00 <81 dd dd> // read status // adjust display with given status information // return from interrupt preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 39 fig. 3?2: software flow diagram for a minimum demodulator setup for a european multistandard set applying the automatic sound select feature write source select settings example: set main source select to "stereo or a" set aux source select to "stereo or b" set scart_out source select to "stereo or a/b" set channel matrix mode for all outputs to "stereo" write 01 into standard select register (start automatic standard detection) write modus register : example for the essential bits: [0] = 1 automatic sound select = on [1] = 1 enable interrupt if status changes [8] = 0 ana_in1+ is selected define preference for automatic standard detection: [12] = 0 if 6.5 mhz, set secam-l [14:13] = 3 ignore 4.5 mhz carrier write fm/am-prescale write nicam-prescale in case of interrupt from msp to controller: read status adjust display if bilingual, adjust source select setting if required result = 0 ? set previous standard or set standard manually according picture information yes no expecting interrupt from msp msp 44x8g-c4 preliminary data sheet 40 march 29, 2004; 6251-623-1pd micronas 4. specifications 4.1. outline dimensions fig. 4?1: psdip64-1: p lastic s hrink d ual i n-line p ackage, 64 leads, 750 mil ordering code: pp weight approximately 8.77 g preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 41 fig. 4?2: pmqfp80-11: p lastic m etric q uad f lat p ackage, 80 leads, 14 20 2.7 mm 3 , high standoff ordering code: qa weight approximately 1.68 g msp 44x8g-c4 preliminary data sheet 42 march 29, 2004; 6251-623-1pd micronas fig. 4?3: pmqfp64-2: p lastic m etric q uad f lat p ackage, 64 leads, 10 10 2 mm 3 ordering code: qi weight approximately 0.5 g preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 43 4.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant obl = obligatory; connect as described in circuit diagram dvss: if not used, connect to dvss ahvss: connect to ahvss pin no. pin name type connection (if not used) short description pmqfp 80-11 pmqfp 64-2 psdip 64-1 1 64 8 nc lv not connected 219i2c_cl in/outobl i 2 c clock 3 2 10 i2c_da in/out obl i 2 c data 4 3 11 i2s_cl in/out lv i 2 s clock 5 4 12 i2s_ws in/out lv i 2 s word strobe 6513i2s_da_outoutlv i 2 s data output 7 6 14 i2s_da_in1 in lv i 2 s1 data input 8 7 15 i2s_da_out4 out lv asynchronous i 2 s4 data output 9 8 16 i2s_ws4 in/out lv asynchronous i 2 s4 word strobe input/output 10 9 17 i2s_cl4 in/out lv asynchronous i 2 s4 clock input/output 11 ?? dvsup obl digital power supply + 5 v 12 ?? dvsup obl digital power supply + 5 v 13 10 18 dvsup obl digital power supply + 5 v 14 ?? dvss obl digital ground 15 ?? dvss obl digital ground 16 11 19 dvss obl digital ground ? 12 20 i2s_da_in2/3 in lv i 2 s2/3-data input 17 ?? i2s_da_in2 in lv pmqfp80-11: pin 22 separate i2s_da_in3 18 13 21 nc lv not connected 19 14 22 i2s_cl3 in lv i 2 s3 clock 20 15 23 i2s_ws3 in lv i 2 s3 word strobe 21 16 24 resetq in obl power-on-reset 22 ?? i2s_da_in3 in lv i 2 s3 data input 23 ?? nc lv not connected 24 17 25 daca_r out lv aux out, right msp 44x8g-c4 preliminary data sheet 44 march 29, 2004; 6251-623-1pd micronas 25 18 26 daca_l out lv aux out, left 26 19 27 vref2 obl reference ground 2 27 20 28 dacm_r out lv main out, right 28 21 29 dacm_l out lv main out, left 29 22 30 nc lv not connected 30 23 31 nc lv not connected 31 24 32 nc lv not connected 32 ?? nc lv not connected 33 25 33 sc2_out_r out lv scart output 2, right 34 26 34 sc2_out_l out lv scart output 2, left 35 27 35 vref1 obl reference ground 1 36 28 36 sc1_out_r out lv scart output 1, right 37 29 37 sc1_out_l out lv scart output 1, left 38 30 38 capl_a obl volume capacitor aux 39 31 39 ahvsup obl analog power supply 8.0 v 40 32 40 capl_m obl volume capacitor main 41 ?? nc lv not connected 42 ?? nc lv not connected 43 ?? ahvss obl analog ground 44 33 41 ahvss obl analog ground 45 34 42 agndc obl analog reference voltage 46 ?? nc lv not connected 47 35 43 sc4_in_l in lv scart 4 input, left 48 36 44 sc4_in_r in lv scart 4 input, right 49 37 45 asg ahvss analog shield ground 50 38 46 sc3_in_l in lv scart 3 input, left 51 39 47 sc3_in_r in lv scart 3 input, right 52 40 48 asg ahvss analog shield ground 53 41 49 sc2_in_l in lv scart 2 input, left 54 42 50 sc2_in_r in lv scart 2 input, right 55 43 51 asg ahvss analog shield ground pin no. pin name type connection (if not used) short description pmqfp 80-11 pmqfp 64-2 psdip 64-1 preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 45 56 44 52 sc1_in_l in lv scart 1 input, left 57 45 53 sc1_in_r in lv scart 1 input, right 58 46 54 vreftop obl reference voltage if a/d converter 59 ?? nc lv not connected 60 47 55 mono_in in lv mono input 61 ?? avss obl analog ground 62 48 56 avss obl analog ground 63 ?? nc lv not connected 64 ?? nc lv not connected 65 ?? avsup obl analog power supply + 5v 66 49 57 avsup obl analog power supply + 5v 67 50 58 ana_in1 + in lv if input 1 68 51 59 ana_in ? in avss via 56 pf / lv if common (can be left vacant, only if if input 1 is also not in use) 69 52 60 ana_in2 + in avss via 56 pf / lv if input 2 (can be left vacant, only if if input 1 is also not in use) 70 53 61 testen in avss test pin 71 54 62 xtal_in in obl crystal oscillator 72 55 63 xtal_out out obl / lv crystal oscillator (see also section 4.3. ?pin descriptions? on page 46) 73 56 64 tp lv test pin 74 57 1 aud_cl_out out lv audio clock output (18.432 mhz) 75 58 2 nc lv not connected 76 59 3 nc lv not connected 77 60 4 d_ctr_i/o_1 in/out lv d_ctr_i/o_1 78 61 5 d_ctr_i/o_0 in/out lv d_ctr_i/o_0; a/v sync in 79 62 6 adr_sel in obl i 2 c bus address select 80 63 7 standbyq in obl stand-by (low-active) pin no. pin name type connection (if not used) short description pmqfp 80-11 pmqfp 64-2 psdip 64-1 msp 44x8g-c4 preliminary data sheet 46 march 29, 2004; 6251-623-1pd micronas 4.3. pin descriptions pin numbers refer to the pmqfp80-11 package. pin 1, nc ? pin not connected. pin 2, i2c_cl ? i 2 c clock input/output (fig. 4?14) via this pin, the i 2 c-bus clock signal has to be sup- plied. the signal can be pulled down by the msp in case of wait conditions. pin 3, i2c_da ? i 2 c data input/output (fig. 4?14) via this pin, the i 2 c-bus data is written to or read from the msp. pin 4, i2s_cl ? i 2 s clock input/output (fig. 4?15) clock line for the synchronous i 2 s bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s clock has to be supplied. pin 5, i2s_ws ? i 2 s word strobe input/output (fig. 4?15) word strobe line for the synchronous i 2 s bus. in mas- ter mode, this line is driven by the msp; in slave mode, an external i 2 s word strobe has to be supplied. pin 6, i2s_da_out1 ? i 2 s data output (fig. 4?19) output of digital serial sound data of the msp on the synchronous i 2 s bus. pin 7, i2s_da_in1 ? i 2 s data input 1 (fig. 4?11) first input of digital serial sound data to the msp via the synchronous i 2 s bus. pin 8, i2s_da_out4 ? async i2s data output (fig. 4?19) output of digital serial sound data from the msp via the asynchronous i 2 s4 bus. pin 9, i2s_ws4 ? async i2s bus word strobe input / output (fig. 4?19) word strobe line for the asynchronous i 2 s4 bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s word strobe has to be supplied. pin 10, i2s_cl4 ? async i2s bus clock input / output (fig. 4?19) clock line for the asynchronous i 2 s4 bus. in master mode, this line is driven by the msp; in slave mode, an external i 2 s clock has to be supplied. pins 11, 12, 13, dvsup* ? digital supply voltage power supply for the digital circuitry of the msp. must be connected to a + 5 v (or +3.3 v only available on request) power supply. pins 14, 15, 16, dvss* ? digital ground ground connection for the digital circuitry of the msp. pin 17, i2s_da_in2 ? i 2 s data input 2 (fig. 4?11) second input of digital serial sound data to the msp via the synchronous i 2 s bus. in all packages except pmqfp80-11, this pin is also connected to the asyn- chronous i 2 s interface 3. pins 18, nc ? pin not connected. pins 19, i2s_cl3 ? i 2 s clock input (fig. 4?11) clock line for the asynchronous i 2 s bus. since only a slave mode is available an external i 2 s clock has to be supplied. pins 20, i2s_ws3 ? i 2 s word strobe input (fig. 4?11) word strobe line for the asynchronous i 2 s bus. since only a slave mode is available an external i 2 s word strobe has to be supplied. pin 21, resetq ? reset input (fig. 4?7) in the steady state, high level is required. a low level resets the msp 44x8g. pin 22, i2s_da_in3 ? i 2 s data input 3 (fig. 4?11) input of digital serial sound data to the msp via the asynchronous i 2 s bus. in all packages except pmqfp80-11, this pin is also connected to synchro- nous i 2 s interface 2. pins 23, nc ? pin not connected. pins 24, 25, daca_r/l ? aux outputs (fig. 4?17) output of the aux signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected aux volume. pin 26, vref2 ? reference ground 2 reference analog ground. this pin must be connected separately to the ground (ahvss). vref2 serves as a clean ground and should be used as the reference for analog connections to the main and aux outputs. pins 27, 28, dacm_r/l ? main outputs (fig. 4?17) output of the main signal. a 1 nf capacitor to ahvss must be connected to these pins. the dc offset on these pins depends on the selected main volume. pin 29, 30, 31, 32 nc ? pin not connected. pins 33, 34, sc2_out_r/l ? scart2 outputs (fig. 4?18) output of the scart2 signal. connections to these pins must use a 100- ? series resistor and are intended to be ac-coupled. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 47 pin 35, vref1 ? reference ground 1 reference analog ground. this pin must be connected separately to the ground (ahvss). vref1 serves as a clean ground and should be used as the reference for analog connections to the scart outputs. pins 36, 37, sc1_out_r/l ? scart1 outputs (fig. 4?18) output of the scart1 signal. connections to these pins must use a 100- ? series resistor and are intended to be ac-coupled. pin 38, capla ? volume capacitor aux (fig. 4?20) a 10- f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for aux volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1- f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sens itive for magnetic induction. pin 39, ahvsup* ? analog power supply high volt- age power is supplied via this pin for the analog circuitry of the msp (except if input). this pin must be connected to the + 8 v supply. (+5 v-operation is possible with restrictions in performance) pin 40, caplm ? volume capacitor main (fig. 4?20) a 10- f capacitor to ahvsup must be connected to this pin. it serves as a smoothing filter for main volume changes in order to suppress audible plops. the value of the capacitor can be lowered to 1 f if faster response is required. the area encircled by the trace lines should be minimized; keep traces as short as possible. this input is sens itive for magnetic induction. pins 41, 42, nc ? pins not connected. pins 43, 44, ahvss* ? analog power supply high voltage ground connection for the analog circuitry of the msp (except if input). pin 45, agndc ? internal analog reference voltage this pin serves as the internal ground connection for the analog circuitry (except if input). it must be con- nected to the vref pins with a 3.3- f and a 100-nf capacitor in parallel. this pi ns shows a dc level of typ- ically 3.73 v (with ahvsup = 8 v). pin 46, nc ? pin not connected. pins 47, 48, sc4_in_l/r ? scart4 inputs (fig. 4?10) the analog input signal for scart4 is fed to this pin. analog input connection must be ac-coupled. pins 49, 52, and 55, asg* ? analog shield ground analog ground (ahvss) shou ld be connected to this pin to reduce cross-coupling between scart inputs. pins 50, 51, sc3_in_l/r ? scart3 inputs (fig. 4?10) the analog input signal for scart3 is fed to this pin. analog input connection must be ac-coupled. pins 53, 54 sc2_in_l/r ? scart2 inputs (fig. 4?10) the analog input signal for scart2 is fed to this pin. analog input connection must be ac-coupled. pins 56, 57 sc1_in_l/r ? scart1 inputs (fig. 4?10) the analog input signal for scart1 is fed to this pin. analog input connection must be ac-coupled. pin 58, vreftop ? reference voltage if a/d con- verter (fig. 4?12) via this pin, the reference voltage for the if a/d con- verter is decoupled. it must be connected to avss pins with a 10- f and a 100-nf capacitor in parallel. traces must be kept short. pin 59, nc ? pin not connected. pin 60 mono_in ? mono input (fig. 4?10) the analog mono input signal is fed to this pin. analog input connection must be ac-coupled. pins 61, 62, avss* ? analog power supply voltage ground connection for the analog if input circuitry of the msp. pins 63, 64, nc ? pins not connected. pins 65, 66, avsup* ? analog power supply voltage power is supplied via this pin for the analog if input cir- cuitry of the msp. this pin must be connected to the + 5 v supply. pin 67, ana_in1 + ? if input 1 (fig. 4?12) the analog sound if signal is supplied to this pin. inputs must be ac-coupled. this pin is designed as symmetrical input: ana_in1 + is internally connected to one input of a symmetrical op amp, ana_in- to the other. pin 68, ana_in ? ? if common (fig. 4?12) this pins serves as a common reference for ana_in1/ 2 + inputs and must be ac-coupled. pin 69, ana_in2 + ? if input 2 (fig. 4?12) the analog sound if signal is supplied to this pin. inputs must be ac-coupled. this pin is designed as symmetrical input: ana_in2 + is internally connected to one input of a symmetrical op amp, ana_in ? to the other. pin 70, testen ? test enable pin (fig. 4?8) this pin enables factory test modes. for normal opera- tion, it must be connected to ground. msp 44x8g-c4 preliminary data sheet 48 march 29, 2004; 6251-623-1pd micronas pins 71, 72 xtal_in, xtal_out ? crystal input and output pins (fig. 4?16) these pins are connected to an 18.432 mhz crystal oscillator which is digitally tuned by integrated capaci- tances. an external clock can be fed into xtal_in (leave xtal_out vacant in this case). the audio clock output signal aud_cl_out is derived from the oscillator. external capacito rs at each crystal pin to ground (avss) are required. it should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. pin 73, tp ? this pin enables factory test modes. for normal operation, it must be left vacant. pin 74, aud_cl_out ? audio clock output (fig. 4?16) this is the 18.432 mhz main clock output. pins 75, 76, nc ? pins not connected. pins 77, 78, d_ctr_i/o_1/0 ? digital control input/ output pins (fig. 4?15) these pins serve as general purpose input/output pins. pin d_ctr_i/o_1 can be used as an interrupt request pin to the controller. d_ctr_i/o_0 can be used as input pin for audi o/video synchronization. pin 79, adr_sel ? i 2 c bus address select (fig. 4?13) by means of this pin, one of three device addresses for the msp can be selected. the pin can be connected to ground (i 2 c device addresses 80/81 hex ), to + 5v sup- ply (84/85 hex ), or left open (88/89 hex ). pin 80, standbyq ? stand-by in normal operation, this pin must be high. if the msp is switched off by first pulling standbyq low and then (after >1 s delay) switching off the 5 v, but keeping the 8-v power supply ( ?stand-by?-mode ), the scart switches maintain their position and function. pin -, i2s_da_in2/3 ? i 2 s data input (see fig. 4?11). this pin is connected to i2s_da_in2 and i2s_da_in3. not available for pmqfp80-11 package. * application note: all ground pins should be connected to one low-resis- tive ground plane. all supply pins should be connected separately with short and low-resistive lines to the power supply. decoupling capacitors from dvsup to dvss, avsup to avss, and ahvsup to ahvss are recommended as closely as possible to these pins. decoupling of dvsup and dvss is most important. we recommend using more than one capacitor. by choosing different values, the frequency range of active decoupling can be extended. in our application boards we use: 220 pf, 470 pf, 1.5 nf, and 10 f. the capacitor with the low- est value should be placed nearest to the pins. the asg pins should be connected as closely as pos- sible to the msp ground. they are intended for leading with the scart signals as sh ield lines and should not be connected to ground at the scart-connector. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 49 4.4. pin configurations fig. 4?4: pmqfp80-11 package 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avsup avsup ana_in1+ ana_in ? ana_in2+ testen xtal_in xtal_out tp aud_cl_out nc nc d_ctr_i/o_1 d_ctr_i/o_0 adr_sel standbyq capl_m ahvsup capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r nc nc nc nc dacm_l dacm_r vref2 daca_l nc avss avss mono_in nc vreftop sc1_in_r sc1_in_l asg nc sc2_in_r sc2_in_l asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l nc agndc ahvss ahvss nc nc i2c_cl i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 i2s_da_out4 i2s_ws4 i2s_cl4 nc dvsup dvsup dvsup dvss dvss dvss i2s_da_in2 nc i2s_cl3 i2s_ws3 resetq i2s_da_in3 nc daca_r msp 44x8g msp 44x8g-c4 preliminary data sheet 50 march 29, 2004; 6251-623-1pd micronas fig. 4?5: pmqfp64-2 package 49 avsup 50 ana_in1+ 51 ana_in ? 52 ana_in2+ 53 testen 54 xtal_in 55 xtal_out 56 tp 57 aud_cl_out 58 nc 59 nc 60 d_ctr_i/o_1 61 c_ctr_i/o_0 62 adr_sel 63 standbyq 64 nc capl_m 32 ahvsup 31 capl_a 30 sc1_out_l 29 sc1_out_r 28 vref1 27 sc2_out_l 26 sc2_out_r 25 nc 24 nc 23 nc 22 dacm_l 21 dacm_r 20 vref2 19 daca_l 18 daca_r 17 mono_in vreftop sc1_in_r sc1_in_l asg sc2_in_r sc2_in_l avss asg sc3_in_r sc3_in_l asg sc4_in_r sc4_in_l agndc ahvss i2c_da i2s_cl i2s_ws i2s_da_out i2s_da_in1 i2s_da_out4 i2s_ws4 i2c_cl i2s_cl4 dvsup dvss i2s_da_in2/3 nc i2s_cl3 i2s_ws3 resetq 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 msp 44x8g preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 51 fig. 4?6: psdip64-1 package 1 aud_cl_out 2 nc 3 nc 4 d_ctr_i/o_1 5 d_ctr_i/o_0 6 adr_sel 7 standbyq 8 nc 9 i2c_cl 10 i2c_da 11 i2s_cl 12 i2s_ws 13 i2s_da_out 14 i2s_da_in1 15 i2s_da_out4 16 i2s_ws4 tp 64 xtal_out 63 xtal_in 62 testen 61 ana_in2+ 60 ana_in ? 59 ana_in+ 58 avsup 57 avss 56 mono_in 55 vreftop 54 sc1_in_r 53 sc1_in_l 52 asg 51 sc2_in_r 50 sc2_in_l 49 17 i2s_cl4 18 dvsup 19 dvss 20 i2s_da_in2/3 21 nc 22 i2s_cl3 23 i2s_ws3 24 resetq 25 daca_r 26 daca_l asg 48 sc3_in_r 47 sc3_in_l 46 asg 45 sc4_in_r 44 sc4_in_l 43 agndc 42 ahvss 41 capl_m 40 ahvsup 39 msp 44x8g vref2 dacm_r dacm_l nc nc nc 38 37 36 35 34 33 27 28 29 30 31 32 capl_a sc1_out_l sc1_out_r vref1 sc2_out_l sc2_out_r msp 44x8g-c4 preliminary data sheet 52 march 29, 2004; 6251-623-1pd micronas 4.5. pin circuits fig. 4?7: input pin: resetq fig. 4?8: input pin: testen fig. 4?9: input pin: mono_in fig. 4?10: input pins: sc4-1_in_l/r fig. 4?11: input pins: i2s_da_in1..3, i2s_cl 3, i2s_ws3, standbyq fig. 4?12: input pins: vreftop, ana_in1 + , ana_in-, ana_in2 + fig. 4?13: input pin: adr_sel dvss >300 k avsup 200 k 3.75 v 24 k ? 3.75 v 40 k ? d a ana_in1+ vreftop ana_in ? ana_in2+ adr_sel gnd dvsup 23 k ? 23 k ? preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 53 fig. 4?14: input/output pins: i2c_cl, i2c_da fig. 4?15: input/output pins: i2s_cl, i2s_ws, d_ctr_i/o_1, d_ctr_i/o_0, i2s_cl4, i2s_ws4 fig. 4?16: input/output pins: xtal_in, xtal_out, aud_cl_out fig. 4?17: output pins: daca_r/l, dacm_r/l fig. 4?18: output pins: sc_2_out_r/l, sc_1_out_r/l fig. 4?19: output pins: i2s_da_out, i2s_da_out4 fig. 4?20: capacitor pins: capl_a, capl_m fig. 4?21: pin: agndc n gnd dvsup p n gnd 3 ? 30 pf 2.5 v 500 k ? 3 ? 30 pf p n gain=0.5 ahvsup 0...1.2 ma 3.3 k ? 26 pf 120 k ? 300 ? 3.75 v dvsup p n gnd 0...2 v 3.75 v 125 k ? msp 44x8g-c4 preliminary data sheet 54 march 29, 2004; 6251-623-1pd micronas 4.6. electrical characteristics abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip 4.6.1. absolute maximum ratings stresses beyond those listed in the ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these conditions is not implied. exposure to absolute maximum rating conditions for extended periods will affect device reliability. this device contains circuitry to protect the inputs and ou tputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso- lute maximum-rated voltages to this high-impedance circuit. all voltages listed are referenced to ground (0 v, v ss ) except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. table 4?1: absolute maximum ratings symbol parameter pin name limit values unit min. max. t a 1) ambient operating temperature psdip64-1 pmqfp80-11 pmqfp64-2 ? 0 70 70 65 c t c case operating temperature psdip64-1 pmqfp80-11 pmqfp64-2 ? 0 85 95 100 c t s storage temperature ?? 40 125 c p max maximum power dissipation psdip64-1 pmqfp80-11 pmqfp64-2 1540 980 1000 mw mw mw v sup1 supply voltage 1 ahvsup ? 0.3 9.0 v v sup2 supply voltage 2 dvsup ? 0.3 6.0 v v sup3 supply voltage 3 avsup ? 0.3 6.0 v v idig input voltage, all digital inputs ? 0.3 v sup2 + 0.3 v i idig input current, all digital pins ?? 20 + 20 ma 1) measured on standard board according to jesd 51 standard with maximum power consumption allowed for this package. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 55 v iana input voltage, all analog inputs scn_in_s, 1) mono_in ? 0.3 v sup1 + 0.3 v i iana input current, all analog inputs scn_in_s, 1) mono_in ? 5 + 5ma i oana output current, all scart outputs scn_out_s 1) 2) 2) i oana output current, all analog outputs except scart outputs dacp_s 1) 2) 2) i cana output current, other pins connected to capacitors capl_p, 1) agndc 2) 2) 1) ?n? means ?1?, ?2?, ?3?, or ?4?, ?s? means ?l? or ?r?, ?p? means ?m? or ?a? 2) the analog outputs are short-circuit proof with respect to supply voltage 1 and ground. table 4?1: absolute maximum ratings, continued symbol parameter pin name limit values unit min. max. msp 44x8g-c4 preliminary data sheet 56 march 29, 2004; 6251-623-1pd micronas 4.6.2. recommended op erating conditions functional operation of the device beyond those indicated in the ?recommended operating conditions/characteris- tics? is not implied and may result in unpredictable behavior , reduce reliability and lifetime of the device. all voltages listed are referenced to ground (v ss = 0 v) except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. do not insert the device into a live socket. instead, apply power by switching on the external power supply. for power-up/-down sequences, see the instructions in section 4.6.3.3. of this document. 4.6.2.1. general recommended operating conditions symbol parameter pin name limit values unit min. typ. max. t a ambient operating temperature psdip64-1 pmqfp80-11 pmqfp64-2 ? 1) 70 70 65 c t c case operating temperature psdip64-1 pmqfp80-11 pmqfp64-2 ? 85 95 100 c v sup1 supply voltage 1 (ahvsup = 8 v) ahvsup 7.6 8.0 8.7 v supply voltage 1 (ahvsup = 5 v) 4.75 5.0 5.25 v v sup2 supply voltage 2 (dvsup = 5 v) dvsup 4.75 5.0 5.25 v supply voltage 2 (dvsup = 3.3 v) 2) 3.15 2) 3.3 2) 3.45 2) v v sup3 supply voltage 3 avsup 4.75 5.0 5.25 v t stbyq1 standbyq setup time before turn-off of second supply voltage standbyq, dvsup 1 s 1) a power-optimized board layout is recommended. the case operating temperatures mentioned in the rec- ommended operating conditions must not be exceeded at worst case conditions of the application. 2) only available on request preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 57 4.6.2.2. analog input and output recommendations symbol parameter pin name limit values unit min. typ. max. c agndc agndc-filter-capacitor agndc ? 20% 3.3 f ceramic capacitor in parallel ? 20% 100 nf c insc dc-decoupling capacitor in front of scart inputs scn_in_s 1) ? 20% 330 nf v insc scart input level 2.0 v rms v inmono input level, mono input mono_in 2.0 v rms r lsc scart load resistance scn_out_s 1) 10 k ? c lsc scart load capacitance 6.0 nf c vma main/aux volume capacitor capl_p 10 f c fma main/aux filter capacitor dacp_s 1) ? 10% 1 + 10% nf 1) ?n? means ?1?, ?2?, ?3?, or ?4?, ?s? means ?l? or ?r?, ?p? means ?m? or ?a? msp 44x8g-c4 preliminary data sheet 58 march 29, 2004; 6251-623-1pd micronas 4.6.2.3. recommendations for analog sound if input signal symbol parameter pin name limit values unit min. typ. max. c vreftop vreftop-filter-capacitor vreftop ? 20% 10 f ceramic capacitor in parallel ? 20% 100 nf f if_fmtv analog input frequency range for tv applications ana_in1 + , ana_in2 + , ana_in ? 09mhz f if_fmradio analog input frequency for fm-radio applications 10.7 mhz v if_fm analog input range fm/nicam 0.1 0.8 3 v pp v if_am analog input range am/nicam 0.1 0.45 0.8 v pp r fmni ratio: nicam carrier/fm carrier (unmodulated carriers) bg: i: ? 20 ? 23 ? 7 ? 10 0 0 db db r amni ratio: nicam carrier/am carrier (unmodulated carriers) ? 25 ? 11 0 db r fm ratio: fm-main/fm -sub satellite 7 db r fm1/fm2 ratio: fm1/fm2 german fm-system 7db r fc ratio: main fm carrier/ color carrier 15 ?? db r fv ratio: main fm carrier/ luma components 15 ?? db pr if passband ripple ?? 2db sup hf suppression of spectrum above 9.0 mhz (not for fm radio) 15 db fm max maximum fm-deviation (approx.) normal mode hdev2: high deviation mode hdev3: very high deviation mode 180 360 540 khz khz khz preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 59 4.6.2.4. crystal recommendations symbol parameter pin name limit values unit min. typ. max. general crystal recommendations f p crystal parallel resonance fre- quency at 12 pf load capacitance 18.432 mhz r r crystal series resistance 8 25 ? c 0 crystal shunt (parallel) capacitance 6.2 7.0 pf c l external load capacitance 1) xtal_in, xtal_out psdip approx. 1.5 pmqfp approx. 3.3 pf pf crystal recommendations for master-slave applications (msp-clock must perform synchronization to i 2 s clock) f tol accuracy of adjustment ? 20 + 20 ppm d tem frequency variation versus temperature ? 20 + 20 ppm c 1 motional (dynamic) capacitance 19 24 ff f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.431 18.433 mhz crystal recommendations for fm / nicam applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment ? 30 + 30 ppm d tem frequency variation versus temperature ? 30 + 30 ppm c 1 motional (dynamic) capacitance 15 ff f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.4305 18.4335 mhz crystal recommendations for all analog fm/am applications (no msp-clock synchronization to i 2 s clock possible) f tol accuracy of adjustment ? 100 + 100 ppm d tem frequency variation versus temperature ? 50 + 50 ppm f cl required open loop clock frequency (t amb = 25 c) aud_cl_out 18.429 18.435 mhz amplitude recommendation for oper ation with external clock input (c load after reset typ. 22 pf) v xca external clock amplitude xtal_in 0.7 v pp 1) external capacitors at each crystal pin to ground are requir ed. they are necessary to tune the open-loop frequency of the internal pll and to stabilize the frequency in closed-loop operation. due to different layouts, the accurate capacitor value should be determined with the customer pcb . the suggested values (1.5...3.3 pf) are figures based on experience and should serve as ?start value?. to adjust the capacitor value, reset the msp. after the reset, no i 2 c telegrams should be transmitted. measure the frequency at aud_cl_out-pin. change the capacitor val ue until the free running frequency matche s 18.432 mhz as closely as possible. the higher the capacity, the lower the resulting clock frequency. note: to minimize adjustment tolerances for all msp-generations, it is strongly recommended to use the so-called msp-xtal- ref ics (available in all packages) for the capacitor adjustment. msp 44x8g-c4 preliminary data sheet 60 march 29, 2004; 6251-623-1pd micronas 4.6.3. characteristics for min./max. values: at t a = 0 to 70 c, f clock = 18.432 mhz v sup1 = 7.6 to 8.7 v (4.75 to 5.25 v if v sup1 = 5 v) v sup2 = 4.75 to 5.25 v (3.15 to 3.45 v if v sup2 = 3.3 v , only available on request) v sup3 = 4.75 to 5.2 v for typical values: at t a = 60 c, f clock = 18.432 mhz v sup1 = 8 v (5 v if noted) v sup2 = 5 v (3.3 v if noted, only available on request) v sup3 = 5 v t j = junction temperature main (m) = main channel, aux (a) = aux channel 4.6.3.1. general characteristics symbol parameter pin name limit valus unit test conditions min. typ. max. supply i sup1a first supply current (active) (ahvsup = 8 v) ahvsup 17 11 25 16 ma ma vol. main and aux = 0 db vol. main and aux = - 30db first supply current (active) (ahvsup = 5 v) 11 8 17 11 ma ma vol. main and aux = 0 db vol. main and aux = -30 db i sup2a second supply current (active) (dvsup = 5 v) dvsup 75 100 ma second supply current (active) (dvsup = 3.3 v) 1) 75 1) 100 1) ma i sup3a third supply current (active) avsup 35 45 ma i sup1s first supply current (ahvsup = 8 v) ahvsup 5.6 7.7 ma standbyq = low first supply current (ahvsup = 5 v) 3.7 5.1 ma clock f clock clock input frequency xtal_in 18.432 mhz d clock clock high to low ratio 45 55 % t jitter clock jitter (verification not provided in production test) 50 ps v xtaldc dc-voltage oscillator 2.5 v t startup oscillator startup time at vdd slew-rate of 1 v/ s xtal_in, xtal_out 0.4 2 ms v aclkac audio clock output ac voltage aud_cl_out 1.2 1.8 v pp load = 40 pf v aclkdc audio clock output dc voltage 0.4 0.6 v sup3 i max = 0.2 ma r outhf_acl hf output resistance 140 ? 1) only available on request preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 61 4.6.3.2. digita l inputs, digital outputs symbol parameter pin name limit valus unit test conditions min. typ. max. digital inputs levels v digil digital input low voltage standbyq d_ctr_i/o_0/1 0.2 v sup2 v digih digital input high voltage 0.5 v sup2 z digi input impedance 5 pf i dleak digital input leakage current ? 11 a0v < u input < dvsup d_ctr_i/o_0/1: tri-state v digil adr_sel input low voltage adr_sel 0.2 v sup2 v digih adr_sel input high voltage 0.8 v sup2 i adrsel input current ? 500 ? 220 au adr_sel = dvss 220 500 au adr_sel = dvsup digital output levels v dctrol digital output low voltage d_ctr_i/o_0 d_ctr_i/o_1 0.4 v iddctr = 1 ma v dctroh digital output high voltage v sup2 ? 0.3 v iddctr = ? 1 ma msp 44x8g-c4 preliminary data sheet 62 march 29, 2004; 6251-623-1pd micronas 4.6.3.3. reset input and power-up fig. 4?22: power-up sequence symbol parameter pin name limit valus unit test conditions min. typ. max. resetq input levels v rhl reset high-low transition voltage resetq 0.3 0.4 v sup2 v rlh reset low-high transition voltage 0.45 v sup2 z res input capacitance 5 pf i res input high current 20 au resetq = dvsup 4.5 v internal reset t/ms resetq avsup dvsup high low t/ms t/ms note: the reset should not reach high level before the oscillator has started. this requires a reset delay of >2 ms 0.45 x dvsup means 2.25 volt with dvsup = 5.0 v 0.3...0.4 dvsup 0.45 dvsup high-to-low threshold low-to-high threshold reset delay >2 ms preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 63 4.6.3.4. i 2 c-bus characteristics fig. 4?23: i 2 c bus timing diagram symbol parameter pin name limit valus unit test conditions min. typ. max. v i2cil i 2 c-bus input low voltage i2c_cl, i2c_da 0.3 v sup2 v i2cih i 2 c-bus input high voltage 0.6 v sup2 t i2c1 i 2 c start condition setup time 120 ns t i2c2 i 2 c stop condition setup time 120 ns t i2c5 i 2 c-data setup time before rising edge of clock 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns t i2c3 i 2 c-clock low pulse time i2c_cl 500 ns t i2c4 i 2 c-clock high pulse time 500 ns f i2c i 2 c-bus frequency 1.0 mhz v i2col i 2 c-data output low voltage i2c_cl, i2c_da 0.4 v i i2col = 3 ma i i2coh i 2 c-data output high leakage current 1.0 av i2coh = 5 v t i2col1 i 2 c-data output hold time after falling edge of clock 15 ns t i2col2 i 2 c-data output setup time before rising edge of clock 100 ns f i2c = 1 mhz i2c_cl i2c_da as input i2c_da as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t i2col1 msp 44x8g-c4 preliminary data sheet 64 march 29, 2004; 6251-623-1pd micronas 4.6.3.5. i 2 s-bus characteristics symbol parameter pin name limit valus unit test conditions min. typ. max. v i2sil input low voltage i2s_cl i2s_ws i2s_cl3 i2s_ws3 i2s_da_in1..3 0.2 v sup2 v i2sih input high voltage 0.5 v sup2 z i2si input impedance 5 pf i leaki2s input leakage current ? 11 a0v < u input < dvsup v i2sol i 2 s output low voltage i2s_cl i2s_ws i2s_da_out 0.4 v i i2sol = 1 ma v i2soh i 2 s output high voltage v sup2 ? 0.3 vi i2soh = ? 1 ma f i2sows i 2 s-word strobe output frequency i2s_ws 48.0 khz f i2socl i 2 s-clock output frequency i2s_cl 1.536 3.072 mhz r i2s10/i2s20 i 2 s-clock output high/low-ratio 0.9 1.0 1.1 synchronous i 2 s interface t s_i2s i 2 s input setup time before rising edge of clock i2s_da_in1/2 i2s_cl 12 ns for details see fig. 4?24 ?i2s timing diagram (syn- chronous interface)? t h_i2s i 2 s input hold time after rising edge of clock 40 ns t d_i2s i 2 s output delay time after falling edge of clock i2s_cl i2s_ws i2s_da_out 28 ns c l =30 pf f i2sws i 2 s-word strobe input frequency i2s_ws 48.0 khz f i2scl i 2 s-clock input frequency i2s_cl 1.536 3.072 mhz r i2scl i 2 s-clock input ratio 0.9 1.1 asynchronous i 2 s input interface t s_i2s3 i 2 s3 input setup time before rising edge of clock i2s_cl3 i2s_ws3 i2s_da_in3 4 ns for details see fig. 4?25 ?i2s3 timing diagram (asynchronous input inter- face)? t h_i2s3 i 2 s3 input hold time after rising edge of clock 40 ns f i2s3ws i 2 s3-word strobe input frequency i2s_ws3 6 49 khz f i2s3cl i 2 s3-clock input frequency i2s_cl3 3.136 mhz r i2s3cl i 2 s3-clock input ratio 0.9 1.1 asynchronous i 2 s output interface t s_i2s4 i 2 s wordstrobe setup time before rising edge of clock i2s_ws4 i2s_cl4 4 ns for details see fig. 4?26 ?i2s4 timing diagram (asynchronous output inter- face)? t h_i2s4 i 2 s wordstrobe hold time after rising edge of clock 40 ns t d_i2s4 i 2 s output delay time after falling edge of clock i2s_cl4 i2s_ws4 i2s_da_out4 28 ns c l =30 pf f i2sws4 i 2 s-word strobe slave frequency i2s_ws4 6 49 khz f i2scl4 i 2 s-clock input frequency i2s_cl4 0.129 3.136 mhz r i2scl4 i 2 s-clock input ratio 0.9 1.1 preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 65 fig. 4?24: i 2 s timing diagram (synchronous interface) data: msb first, i 2 s synchronous master r lsb l lsb r lsb l lsb 16/32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16/32 bit right channel 16/32 bit left channel 16/32 bit left channel 1/f i2sws i2s_cl detail c i2s_ws as input i2s_ws as output 1/f i2scl t s_i2s t d_i2s detail a,b i2s_cl i2s_da_out t d_i2s data: msb first, i 2 s synchronous slave r lsb l lsb r lsb l lsb 16, 18...32 bit right channel l lsb l lsb r msb r msb detail c i2s_ws i2s_cl i2s_da_in* ) detail a modus[6] = 1 modus[6] = 0 detail b r lsb r lsb l msb l msb i2s_da_out 16, 18...32 bit right channel 16, 18...32 bit left channel 16,18...32 bit left channel 1/f i2sws t h_i2s t s_i2s i2s_da_in 1) note: 1) i2s_da_in can be ? i2s_da_in1, ? i2s_da_in2, or ? i2s_da_in2/3 msp 44x8g-c4 preliminary data sheet 66 march 29, 2004; 6251-623-1pd micronas fig. 4?25: i 2 s3 timing diagram (asynchronous input interface) fig. 4?26: i 2 s4 timing diagram (asynchronous output interface) right aligned (i 2 s_config[11] = 1, i 2 s_config[9] = 0) 16 bit data & 16...32 clocks allowed i2s_ws3 i2s_cl3 i2s_da_in3 msb 1/f i2s3ws 1/f i2s3cl i2s_cl3 i2s_da_in3 i2s_ws3 t h_i2s3 right sample (i 2 s_config[10] = 0) right sample (i 2 s_config[10] = 1) left sample (i 2 s_config[10] = 0) left sample (i 2 s_config[10] = 1) msb lsb msb msb lsb i2s_da_in3 i2s_da_in3 msb marked (i 2 s_config[9] = 0) lsb marked (i 2 s_config[9] = 1) 16,18...32 bit data & clocks allowed 16,18...32 bit data & clocks allowed t s_i2s3 t s_i2s3 i2s_ws4 i2s_cl4 i2s_da_out4 msb 1/f i2s4ws right sample (i 2 s_config2[2] = 0) right sample (i 2 s_config2[2] = 1) left sample (i 2 s_config2[2] = 0) left sample (i 2 s_config2[2] = 1) msb msb msb i2s_da_out4 msb marked (i 2 s_config2[1] = 0) lsb marked (i 2 s_config2[1] = 1) 16 / 32 bit data & clocks allowed 16 / 32 bit data & clocks allowed i2s_cl4 i2s_da_out4 t d_i2s4 t s_i2s4 i2s_ws4 1/f i2s4cl preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 67 4.6.3.6. analog baseband i nputs and outputs, agndc symbol parameter pin name limit valus unit test conditions min. typ. max. analog ground v agndc0 agndc open circuit voltage (ahvsup =8 v) agndc 3.77 v r load 10 m ? agndc open circuit voltage (ahvsup = 5 v) 2.51 v r outagn agndc output resistance (ahvsup = 8 v) 70 125 180 k ? 3 v v agndc 4 v agndc output resistance (ahvsup = 5 v) 47 83 120 k ? analog input resistance r insc scart input resistance from t a = 0 to 70 c scn_in_s 1) 25 40 58 k ? f signal = 1 khz, i = 0.05 ma r inmono mono input resistance from t a = 0 to 70 c mono_in 152435k ? f signal = 1 khz, i = 0.1 ma 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r? msp 44x8g-c4 preliminary data sheet 68 march 29, 2004; 6251-623-1pd micronas audio analog-to-digital-converter v aicl analog input clipping level for analog-to-digital- conversion (ahvsup = 8 v) scn_in_s, 1) mono_in 2.00 2.25 v rms f signal = 1 khz analog input clipping level for analog-to-digital- conversion (ahvsup = 5 v) 1.13 1.51 v rms scart outputs r outsc scart output resistance scn_out_s 1) 200 200 330 460 500 ? ? f signal = 1 khz, i = 0.1 ma t j = 27 c t a = 0 to 70 c dv outsc deviation of dc-level at scart output from agndc voltage ? 70 + 70 mv a sctosc gain from analog input to scart output scn_in_s, 1) mono_in scn_out_s 1) ? 1.0 + 0.5 db f signal = 1 khz f rsctosc frequency response from analog input to scart output ? 0.5 + 0.5 db with resp. to 1 khz bandwidth: 0 to 20000 hz v outsc signal level at scart output (ahvsup = 8 v) scn_out_s 1) 1.8 1.9 2.0 v rms f signal = 1 khz volume 0 db full scale input from i 2 s signal level at scart output (ahvsup = 5v) 1.17 1.27 1.37 v rms main and aux outputs r outma main/aux output resistance dacp_s 1) 2.1 2.1 3.3 4.6 5.0 k ? k ? f signal = 1 khz, i = 0.1 ma t j = 27 c t a = 0 to 70 c v outdcma dc-level at main/aux-output (ahvsup = 8 v) 1.80 2.04 61 2.28 v mv volume 0 db volume ? 30 db dc-level at main/aux-output (ahvsup = 5 v) 1.12 1.36 40 1.60 v mv volume 0 db volume ? 30 db v outma signal level at main/aux-output (ahvsup = 8 v) 1.23 1.37 1.51 v rms f signal = 1 khz volume 0 db full scale input from i 2 s signal level at main/aux-output (ahvsup = 5 v) 0.76 0.90 1.04 v rms 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? symbol parameter pin name limit valus unit test conditions min. typ. max. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 69 4.6.3.7. sound if inputs 4.6.3.8. power supply rejection symbol parameter pin name limit valus unit test conditions min. typ. max. r ifin input impedance ana_in1 + , ana_in2 + , ana_in ? 1.5 6.8 2 9.1 2.5 11.4 k ? k ? gain agc = 20 db gain agc = 3 db dc vreftop dc voltage at vreftop vreftop 2.45 2.65 2.75 v dc ana_in dc voltage on if inputs ana_in1 + , ana_in2 + , ana_in ? 1.3 1.5 1.7 v xtalk if crosstalk attenuation ana_in1 + , ana_in2 + , ana_in ? 40 db f signal = 1 mhz input level = ? 2 dbr bw if 3 db bandwidth 10 mhz agc agc step width 0.85 db symbol parameter pin name limit valus unit test conditions min. typ. max. psrr: rejection of noise on ahvsup at 1 khz psrr agndc agndc 80 db from analog input to i 2 s output mono_in, scn_in_s 1) 70 db from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 70 db from i 2 s input to scart output scn_out_s 1) 60 db from i 2 s input to main/aux output dacp_s 1) 80 db 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? msp 44x8g-c4 preliminary data sheet 70 march 29, 2004; 6251-623-1pd micronas 4.6.3.9. analog performance symbol parameter pin name limit valus unit test conditions min. typ. max. specifications for ahvsup = 8 v snr dynamic range and signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 90 95 db input level = ? 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 93 96 db input level = ? 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 90 95 db from i 2 s input to main/aux-output for analog volume at 0 db for analog volume at ? 30 db dacp_s 1) 90 83 95 88 db db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.008 0.03 % input level = ? 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s scn_out_s 1) 0.008 0.03 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.008 0.03 % from i 2 s input to main or aux out- put dacp_s 1) 0.008 0.03 % 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 71 specifications for ahvsup = 5 v snr dynamic range and signal-to-noise ratio from analog input to i 2 s output mono_in, scn_in_s 1) 87 92 db input level = ? 20 db with resp. to v aicl , f sig = 1 khz, a-weighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s 1) scn_out_s 1) 90 93 db input level = ? 20 db, f sig = 1 khz, a-weighted 20 hz...20 khz volume = 0 db from i 2 s input to scart output scn_out_s 1) 87 92 db from i 2 s input to main/aux-output for analog volume at 0 db for analog volume at ? 30 db dacp_s 1) 87 75 92 80 db db thd total harmonic distortion from analog input to i 2 s output mono_in, scn_in_s 1) 0.03 0.1 % input level = ? 3 dbr with resp. to v aicl , f sig = 1 khz, unweighted 20 hz...20 khz from analog input to scart output mono_in, scn_in_s scn_out_s 1) 0.1 % input level = ? 3 dbr, f sig = 1 khz, unweighted 20 hz...20 khz from i 2 s input to scart output scn_out_s 1) 0.1 % from i 2 s input to main or aux out- put dacp_s 1) 0.1 % 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? symbol parameter pin name limit valus unit test conditions min. typ. max. msp 44x8g-c4 preliminary data sheet 72 march 29, 2004; 6251-623-1pd micronas crosstalk specifications xtalk crosstalk attenuation input level = ? 3 db, f sig = 1 khz, unused analog inputs connected to ground by z < 1 k ? between left and right channel within scart input/output pair (l r, r l) scn_in scn_out 1) sc1_in or sc2_in i 2 s output sc3_in i 2 s output i 2 s input scn_out 1) 80 80 80 80 db db db db unweighted 20 hz...20 khz between left and right channel within main or aux output pair i 2 s input dacp 1) 75 db unweighted 20 hz...20 khz between scart input/output pairs 1) d = disturbing program o = observed program d: mono/scn_in scn_out o: mono/scn_in scn_out 1) d: mono/scn_in scn_out or unsel. o: mono/scn_in i 2 s output d: mono/scn_in scn_out o: i 2 s input scn_out 1) d: mono/scn_in unselected o: i 2 s input sc1_out 1) 100 95 100 100 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel crosstalk between main and aux output pairs i 2 s input dsp dacp 1) 90 db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel xtalk crosstalk from main or aux output to scart output and vice versa d = disturbing program o = observed program d: mono/scn_in/dsp scn_out o: i 2 s input dacp 1) d: mono/scn_in/dsp scn_out o: i 2 s input dacp 1) d: i 2 s input dacp o: mono/scn_in scn_out 1) d: i 2 s input dacm o: i 2 s input scn_out 1) 80 85 95 95 db db db db (unweighted 20 hz...20 khz) same signal source on left and right disturbing chan- nel, effect on each observed output channel scart output load resis- tance 10 k ? scart output load resis- tance 30 k ? 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? symbol parameter pin name limit valus unit test conditions min. typ. max. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 73 4.6.3.10. sound standard dependent characteristics symbol parameter pin name limit valus unit test conditions min. typ. max. nicam characteristics (msp standard code = 8) dv nicamout tolerance of output voltage of nicam baseband signal dacp_s scn_out_s 1) ? 1.5 + 1.5 db 2.12 khz, modulator input level = 0 dbref s/n nicam s/n of nicam baseband signal 72 db nicam: ? 6 db, 1 khz, rms unweighted 0 to 15 khz, vol = 9 db nic_presc = 7fh output level 1 v rms at dacp_s thd nicam total harmonic distortion + noise of nicam baseband signal 0.1 % 2.12 khz, modulator input level = 0 dbref ber nicam nicam: bit error rate 1 10 ? 7 fm + nicam, norm conditions fr nicam nicam frequency response, 20...15000 hz ? 1.0 + 1.0 db modulator input level = ? 12 db dbref; rms xtalk nicam nicam crosstalk attenuation (dual) 80 db sep nicam nicam channel separation (stereo) 80 db fm characteristics (msp standard code = 3) dv fmout tolerance of output voltage of fm demodulated signal dacp_s, scn_out_s 1) ? 1.5 + 1.5 db 1 fm-carrier, 50 s, 1 khz, 40 khz deviation; rms s/n fm s/n of fm demodulated signal 73 db 1 fm-carrier 5.5 mhz, 50 s, 1 khz, 40 khz devi- ation; rms, unweighted 0 to 15 khz (for s/n); full input range, fm-pres- cale=46h, vol=0db output level 1 v rms at dacp_s thd fm total harmonic distortion + noise of fm demodulated signal 0.1 % fr fm fm frequency responses, 20...15000 hz ? 1.0 + 1.0 db 1 fm-carrier 5.5 mhz, 50 s, modulator input level = ? 14.6 dbref; rms xtalk fm fm crosstalk attenuation (dual) 80 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; bandpass 1 khz sep fm fm channel separation (ste reo) 50 db 2 fm-carriers 5.5/5.74 mhz, 50 s, 1 khz, 40 khz deviation; rms 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? 2) eim refers to 75- s equivalent input modulation. it is defined as the audi o-signal level which results in a stated percentage modulation, when the dbx encoding proc ess is replaced by a 75- s preemphasis network. msp 44x8g-c4 preliminary data sheet 74 march 29, 2004; 6251-623-1pd micronas am characteristics (msp standard code = 9) s/n am(1) s/n of am demodulated signal measurement condition: rms/flat dacp_s, scn_out_s 1) 55 db sif level: 0.1 ? 0.8 v pp am-carrier 54% at 6.5 mhz vol = 0 db, fm/am prescaler set for output = 0.5 v rms at main out; standard code = 09 hex no video/chrominance components s/n am(2) s/n of am demodulated signal measurement condition: qp/ccir 45 db thd am total harmonic distortion + noise of am demodulated signal 0.6 % fr am am frequency response 50 hz... 12 khz ? 2.5 + 1.0 db btsc characteristics (msp standard code = 20 hex , 21 hex ) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacp_s, scn_out_s 1) 68 57 db db 1 khz l or r or sap, 100% modulation, 75 s deem- phasis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.1 0.5 % % 1 khz l or r or sap, 100% 75 s eim 2) , dbx nr or mnr, rms unweighted 0 to 15 khz fr dbx frequency response of btsc ste- reo, 50 hz...12 khz frequency response of btsc- sap, 50 hz...9 khz ? 1.0 ? 1.0 1.0 1.0 db db l or r or sap, 1%...66% eim 2) , dbx nr fr mnr frequency response of btsc ste- reo, 50 hz...12 khz ? 2.0 2.0 db l or r 5%...66% eim 2) , mnr frequency response of btsc- sap, 50 hz...9 khz ? 2.0 2.0 db sap, white noise, 10% modulation, mnr xtalk btsc stereo sap sap stereo 76 80 db db 1 khz l or r or sap, 100% modulation, 75 s deem- phasis, bandpass 1 khz sep dbx stereo separation dbx nr 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr sep mnr stereo separation mnr 30 db l = 300 hz, r = 3.1 khz 14% modulation, mnr fm pil pilot deviation threshold stereo off on stereo on off ana_in1+, ana_in2+ 3.2 1.2 3.5 1.5 khz khz 4.5 mhz carrier modulated with f h = 15.734 khz sif level = 100 mv pp indication: status bit[6] f pilot pilot frequency range 15.563 15.843 khz standard btsc stereo sig- nal, sound carrier only symbol parameter pin name limit valus unit test conditions min. typ. max. 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? 2) eim refers to 75- s equivalent input modulation. it is defined as the audi o-signal level which results in a stated percentage modulation, when the dbx encoding proc ess is replaced by a 75- s preemphasis network. preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 75 btsc characteristics (msp standard code = 20 hex , 21 hex ) with a minimum if input signal level of 70 mvpp (measured without any video/chroma signal components) s/n btsc s/n of btsc stereo signal s/n of btsc-sap signal dacp_s, scn_out_s 1) 64 55 db db 1 khz l or r or sap, 100% modulation, 75 s deem- phasis, rms unweighted 0 to 15 khz thd btsc thd + n of btsc stereo signal thd + n of btsc sap signal 0.15 0.8 % % 1 khz l or r or sap, 100% 75 s eim 2) , dbx nr or mnr, rms unweighted 0 to 15 khz fr dbx frequency response of btsc ste- reo, 50 hz...12 khz frequency response of btsc- sap, 50 hz...9 khz ? 1.0 ? 1.0 1.0 1.0 db db l or r or sap, 1%...66% eim 2) , dbx nr fr mnr frequency response of btsc ste- reo, 50 hz...12 khz ? 2.0 2.0 db l or r 5%...66% eim 2) , mnr frequency response of btsc- sap, 50 hz...9 khz ? 2.0 2.0 db sap, white noise, 10% modulation, mnr xtalk btsc stereo sap sap stereo 75 75 db db 1 khz l or r or sap, 100% modulation, 75 s deem- phasis, bandpass 1 khz sep dbx stereo separation dbx nr 50 hz...10 khz 50 hz...12 khz 35 30 db db l or r 1%...66% eim 2) , dbx nr sep mnr stereo separation mnr 30 db l = 300 hz, r = 3.1 khz 14% modulation, mnr eia-j characteristics (msp standard code = 30 hex ) s/n eiaj s/n of eia-j stereo signal s/n of eiaj sub-channel dacp_s, scn_out_s 1) 60 60 db db 1 khz l or r, 100% modulation, 75 s deemphasis, rms unweighted 0 to 15 khz thd eiaj thd + n of eia-j stereo signal thd + n of eia-j sub-channel 0.2 0.3 % % fr eiaj frequency response of eia-j stereo, 50 hz...12 khz frequency response of eia-j sub- channel, 50 hz...12 khz ? 1.0 ? 1.0 1.0 1.0 db db 100% modulation, 75 s deemphasis xtalk eiaj main sub sub main 66 80 db db 1 khz l or r, 100% modu- lation, 75 s deemphasis, bandpass 1 khz sep eiaj stereo separation 50 hz...5 khz 50 hz...10 khz 35 28 db db eia-j stereo signal, l or r 100% modulation symbol parameter pin name limit valus unit test conditions min. typ. max. 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? 2) eim refers to 75- s equivalent input modulation. it is defined as the audi o-signal level which results in a stated percentage modulation, when the dbx encoding proc ess is replaced by a 75- s preemphasis network. msp 44x8g-c4 preliminary data sheet 76 march 29, 2004; 6251-623-1pd micronas 4.6.3.11. audio/video synchr onization characteristics fm-radio characteristics (msp standard code = 40 hex ) s/n ukw s/n of fm-radio stereo signal dacp_s, scn_out_s 1) 70 db 1 khz l or r, 100% modu- lation, 75 s deemphasis, rms unweighted 0 to 15 khz thd ukw thd + n of fm-radio stereo signal 0.1 % fr ukw frequency response of fm-radio stereo 50 hz...15 khz ? 1.0 +1.0 db l or r, 1%...100% modula- tion, 75 s deemphasis sep ukw stereo separation 50 hz...15 khz 45 db f pilot pilot frequency range ana_in1+ ana_in2+ 18.844 19.125 khz standard fm radio stereo signal symbol parameter pin name limit valus unit test conditions min. typ. max. 1) ?n? means ?1?, ?2?, ?3?, or ?4?; ?s? means ?l? or ?r?; ?p? means ?m? or ?a? 2) eim refers to 75- s equivalent input modulation. it is defined as the audi o-signal level which results in a stated percentage modulation, when the dbx encoding proc ess is replaced by a 75- s preemphasis network. symbol tv or film standard frequency limit valus unit test conditions min. typ. max. a/v sync frequency range for automatic video standard detection pal / secam 50 hz 47.5 52.5 hz ntsc 59.94 hz 57.5 62.5 hz monochrome 60 hz 57.5 62.5 hz a/v sync frequency range check pal / secam 50 hz 45 55 hz ntsc 59.94 hz 55 65 hz monochrome 60 hz 55 65 hz preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 77 5. appendix a: overview of tv-sound standards 5.1. nicam 728 table 5?1: summary of nicam 728 sound modulation parameters specification i b/g l d/k carrier frequency of digital sound 6.552 mhz 5.85 mhz 5.85 mhz 5.85 mhz transmission rate 728 kbit/s type of modulation different ially encoded quad rature phase shift keying (dqpsk) spectrum shaping roll-off factor by means of roll-off filters 1.0 0.4 0.4 0.4 carrier frequency of analog sound component 6.0 mhz fm mono 5.5 mhz fm mono 6.5 mhz am mono 6.5 mhz fm mono terrestrial cable power ratio between vision carrier and analog sound carrier 10 db 13 db 10 db 16 db 13 db power ratio between analog and modulated digital sound carrier 10 db 7 db 17 db 11 db china/ hungary poland 12 db 7 db table 5?2: summary of nicam 728 sound coding characteristics characteristics values audio sampling frequency 32 khz number of channels 2 initial resolution 14 bit/sample companding characteristics near instantaneous, with compre ssion to 10 bits/sample in 32-samples (1 ms) blocks coding for compressed samples 2?s complement preemphasis ccitt recommendation j.17 (6.5 db attenuation at 800 hz) audio overload level + 12 dbm measured at the unity gain frequency of the preemphasis network (2 khz) msp 44x8g-c4 preliminary data sheet 78 march 29, 2004; 6251-623-1pd micronas 5.2. a2-systems table 5?3: key parameters for a2 systems of standards b/g, d/k, and m characteristics sound carrier fm1 sound carrier fm2 tv-sound standard b/g d/k m b/g d/k m carrier frequency in mhz 5.5 6.5 4.5 5.7421875 6.2578125 6.7421875 5.7421875 4.724212 vision/sound power difference 13 db 20 db sound bandwidth 40 hz to 15 khz preemphasis 50 s 75 s 50 s 75 s frequency deviation (nom/max) 27 / 50 khz 17 / 25 khz 27 / 50 khz 15 / 25 khz transmission modes mono transmission mono mono stereo transmission (l + r)/2 (l + r)/2 r (l ? r)/2 dual sound transmission language a language b identification of transmission mode pilot carrier frequency 54.6875 khz 55.0699 khz max. deviation portion 2.5 khz type of modulation / modulation depth am / 50% modulation frequency mono: unmodulated stereo: 117.5 hz dual: 274.1 hz 149.9 hz 276.0 hz preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 79 5.3. btsc-sound system 5.4. japanese fm stereo system (eia-j) table 5?4: key parameters for btsc-sound systems aural carrier btsc-mpx-components (l + r) pilot (l ? r) sap prof. ch. carrier frequency (f hntsc = 15.734 khz) (f hpal = 15.625 khz) 4.5 mhz baseband f h 2 f h 5 f h 6.5 f h sound bandwidth in khz 0.05 - 15 0.05 - 15 0.05 - 10 0.05 - 3.4 preemphasis 75 s dbx dbx 150 s max. deviation to aural carrier 73 khz (total) 25 khz 1) 5 khz 50 khz 1) 15 khz 3 khz max. freq. deviation of subcarrier modulation type am 10 khz fm 3khz fm 1) sum does not exceed 50 khz due to interleaving effects table 5?5: key parameters for japanese fm-stereo sound system eia-j aural carrier fm eia-j-mpx- components (l + r) (l ? r) identification carrier frequency (f h = 15.734 khz) 4.5 mhz baseband 2 f h 3.5 f h sound bandwidth 0.05 - 15 khz 0.05 - 15 khz ? preemphasis 75 s75 s none max. deviation portion to aural carrier 47 khz 25 khz 20 khz 2 khz max. freq. deviation of subcarrier modulation type 10 khz fm 60% am transmitter-sided delay 20 s0 s0 s mono transmission l + r ? unmodulated stereo transmission l + rl ? r 982.5 hz bilingual transmission language a language b 922.5 hz msp 44x8g-c4 preliminary data sheet 80 march 29, 2004; 6251-623-1pd micronas 5.5. fm satellite sound 5.6. fm-stereo radio table 5?6: key parameters for fm satellite sound carrier frequency maximum fm deviation sound mode bandwidth deemphasis 6.5 mhz 85 khz mono 15 khz 50 s 7.02/7.20 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.38/7.56 mhz 50 khz mono/stereo/bilingual 15 khz adaptive 7.74/7.92 mhz 50 khz mono/stereo/bilingual 15 khz adaptive table 5?7: key parameters for fm-stereo radio systems aural carrier fm-radio-mpx-components (l + r) pilot (l ? r) rds/ari carrier frequency (f p = 19 khz) 10.7 mhz baseband f p 2 f p 3 f p sound bandwidth in khz 0.05 - 15 0.05 - 15 preemphasis: ? usa ? europe 75 s 50 s 75 s 50 s max. deviation to aural carrier 75 khz (100%) 90% 1) 10% 90% 1) 5% 1) sum does not exceed 90% due to interleaving effects preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 81 6. appendix b: manual mode to adapt the modes of the standard select regis- ter to individual requirements, the msp 44x8g offers a manual mode, which provides sophisticated program- ming of the msp 44x8g. the manual mode can be used only in those cases, where user specific requirements concerning detec- tion, identification, or carrier positioning have to be met. after the setting of the standard select register, the msp 44x8g is set up for optimal behavior. there- fore, it is not recommended to use the manual mode. 6.1. demodulator write and read registers for manual mode in case of automatic sound select (modus[0]=1), any modifications of all dco registers listed in table 6?1 are ignored. table 6?1: demodulator write registers; subaddress: 10 hex ; these registers are not readable! demodulator write registers address (hex) msp- version description reset mode page auto_fm/am 00 21 4418, 4458 1. modus[0]=1 (automatic sound select): switching level threshold of automatic switching between nicam and fm/am in case of bad nicam reception 2. modus[0]=0 (manual mode): activation and configuration of automatic switching between nicam and fm/am in case of bad nicam reception 00 00 hex 82 a2_threshold 00 22 a2 stereo identification threshold 01 90 hex 84 cm_threshold 00 24 carrier-mute threshold 00 2a hex 84 dco1_lo dco1_hi dco2_lo dco2_hi 00 93 00 9b 00 a3 00 ab note: modifications are ignored fo r automatic sound select = on (modus[0]=1) increment channel 1 low part increment channel 1 high part increment channel 2 low part increment channel 2 high part 00 00 hex 85 note: all registers except auto_fm/am, a2 _threshold, and cm_threshold are initia lized during standard selection and are automatically updated when automatic sound select (modus[0]=1) is on. table 6?2: demodulator read registers; subaddress: 11 hex ; these registers are not writable! demodulator read registers address (hex) msp- version description page c_ad_bits 00 23 4418, 4458 nicam-sync bit, nicam-c-bits, and bit[2:0] of additional data bits 86 add_bits 00 38 nicam: bit[10:3] of additional data bits 86 cib_bits 00 3e nicam: cib1 and cib2 control bits 86 error_rate 00 57 nicam error rate, updated with 182 ms 86 msp 44x8g-c4 preliminary data sheet 82 march 29, 2004; 6251-623-1pd micronas 6.2. dsp write and read registers for manual mode 6.3. manual mode: description of demodulator write registers 6.3.1. automatic switch ing between nicam and analog sound in case of bad nicam reception or loss of the nicam-carrier, the msp 44x8g offers an automatic switching (fall back) to the analog sound (fm/am- mono), without the necessity for the controller of reading and evaluating any parameters. if a proper nicam sig- nal returns, switching back to this source is performed automatically as well. the feature evaluates the nicam error_rate and switches, if necessary, all output channels which are assigned to the nicam-source, to the analog source, and vice versa. an appropriate hysteresis algorithm avoids oscillating effects (see fig. 6?1). status[9] and c_ad_bits[11] (addr: 0023 hex) provide information about the actual nicam-fm/am-status. fig. 6?1: hysteresis for automatic switching 6.3.1.1. function in automatic sound select mode the automatic sound select feature (modus[0]=1) includes the procedure mentioned above. by default, the internal error_rate threshold is set to 700 dec . i.e.: ?nicam analog sound if error_rate > 700 ? analog sound nicam if error_rate < 700/2 table 6?3: dsp-write registers; subaddress: 12 hex , all registers are readable as well write register address (hex) bits operational modes and adjustable range reset mode page additional channel matrix modes 00 08 00 09 00 0a 00 41 00 0b 00 0c [7:0] [sum/diff, ab_xchange, phase_change_b, phase_change_a, a_only, b_only] 00 hex 87 fm fixed deemphasis 00 0f [15:8] [50 s, 75 s, j17, off] off 87 fm adaptive deemphasis [7:0] [off, wp1] off 87 identification mode 00 15 [7:0] [b/g, m] b/g 87 table 6?4: dsp read registers; subaddress: 13 hex , all registers are not writable additional read registers address (hex) bits output range page stereo detection register for a2 stereo systems 00 18 [15:8] [80 hex ... 7f hex ] 8 bit two?s complement 88 dc level readout fm1/ch2-l 00 1b [15:0] [8000 hex ... 7fff hex ] 16 bit two?s complement 88 dc level readout fm2/ch1-r 00 1c [15:0] [8000 hex ... 7fff hex ] 16 bit two?s complement 88 error_rate selected sound nicam analog sound threshold threshold/2 preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 83 the error_rate value of 700 corresponds to a ber of approximately 5.46*10 -3 /s. individual configuration of the threshold can be done using table 6?5. however, the internal setting used by the standard selection is recommended. the optimum nicam sound can be assigned to the msp output channels by selecting one of the ?stereo or a/b?, ?stereo or a?, or ?stereo or b? source channels 6.3.1.2. function in manual mode if the manual mode (modus[0]=0) is required, the activation and configuration of the automatic switching feature has to be done as described in table 6?6. note, that the channel matrix of the corresponding out- put-channels must be set according to the nicam-mode and need not to be changed in the fm/ am-fallback case. example: required threshold = 500: bits[10:1] = 00 1111 1010 table 6?5: coding of automatic nicam/analog sound switching; automatic sound select is on (modus[0] = 1) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 1) 1 default automatic switching with internal threshold bit[11:0] = 0 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = 0 bit[10:1] = 25...1000 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000 3 forced analog mono bit[11] = 1 bit[10:1] = ignored bit[0] = 1 always fm/am 1) the nicam path may be assigned to ?stereo or a/b?, ?stereo or a?, or ?stereo or b? source channels (see table 2?2 on page 13). table 6?6: coding of automatic nicam/analog sound switching; automatic sound select is off (modus[0] = 0) mode description auto_fm [11:0] addr. = 00 21 hex error_rate- threshold/dec source select: input at nicam path 0 reset status forced nicam (automatic switching disabled) bit[11] = 0 bit[10:1] = 0 bit[0] = 0 none always nicam; mute in case of no nicam available 1 automatic switching with internal threshold (default, if automatic sound select is on) bit[11] = 0 bit[10:1] = 0 bit[0] = 1 700 nicam or fm/am, depending on error_rate 2 automatic switching with external threshold (customizing of automatic sound select) bit[11] = 0 bit[10:1] = 25...1000 = threshold/2 bit[0] = 1 set by customer; recommended range: 50...2000 3 forced analog mono (automatic switching disabled) bit[11] = 1 bit[10:1] = 0 bit[0] = 1 none always fm/am msp 44x8g-c4 preliminary data sheet 84 march 29, 2004; 6251-623-1pd micronas 6.3.2. a2 threshold the threshold between st ereo/bilingual and mono identification for the a2 standard has been made pro- grammable according to the user?s preferences. an internal hysteresis ensur es robustness and stability. 6.3.3. carrier-mute threshold the carrier-mute threshold has been made program- mable according to the users preferences. an internal hysteresis ensures stable behavior. table 6?7: write register on i 2 c subaddress 10 hex : a2 threshold register address function name thresholds 00 22 hex (write) a2 threshold register defines threshold of all a2 and eia_j standards for stereo and bilingual detection bit[15:0] 07f0 hex force mono identification ... 0190 hex default setting after reset ... 00a0 hex minimum threshold for stable detection recommended range: 00a0 hex ...03c0 hex a2_thresh table 6?8: write register on i 2 c subaddress 10 hex : carrier-mute threshold register address function name thresholds 00 24 hex (write) carrier-mute threshold register defines threshold for the carrier mute feature bit[15:0] 0000 hex carrier-mute always on (both channels muted) ... 002a hex default setting after reset ... 07ff hex carrier-mute always off (both channels forced on) recommended range: 0014 hex ...0050 hex cm_thresh preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 85 6.3.4. dco-registers note: the use of this register is not recommended. it should be used only in cases where non-stan- dard carrier frequencies have to be processed. please note, that the usage of user specific demodulation frequencies is not possible in combination with the automatic sound select (modus[0]=1). when selecting a tv-sound standard by means of the standard select register, all frequency tuning is performed automatically. if manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequen- cies of the quadrature mixers can be written manually into the msp. in table 6?9, examples for dco register programming are listed. it is necessary to separate these registers into two categories: low part and high part. the formula for the calculation of the incr val- ues for any chosen if frequency is as follows: incr dec = int (f / fs ? 2 24 ) with: int = integer function f = if frequency in mhz f s = sampling frequency (18.432 mhz) conversion of incr into hex-format and separation of the 12-bit low and high parts lead to the required regis- ter values (dco1_hi and _lo for msp-ch1, dco2_hi and _lo for msp-ch2). 6.4. manual mode: description of demodulator read registers note: using the standard selection register together with the status register provides a more economic way to program the msp 44x8g and to retrieve information from the msp. all registers except c_ad_bits are 8 bits wide. they can be read out of the ram of the msp 44x8g. all transmissions take place in 16-bit words. the valid 8-bit data are the 8 lsbs of the received data word. if the automatic sound select feature is not used, the nicam or fm-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. the fm-identification registers are described in section 6.6.1. to handle the nicam-sound and to observe the nicam-quality, at least the registers c_ad_bits and error_rate must be read and evaluated by the controller. addi- tional data bits and cib bits, if supplied by the nicam transmitter, can be obtained by reading the registers add_bits and cib_bits. table 6?9: dco registers for the msp 44x8g; reset status: dco_hi/lo = ?00 00? dco1_lo 00 93 hex , dco1_hi 00 9b hex ; dco2_lo 00 a3 hex , dco2_hi 00 ab hex if-freq. [mhz] dco_hi [hex] dco_lo [hex] if-freq. [mhz] dco_hi [hex] dco_lo [hex] 4.5 03e8 0000 5.04 5.5 5.58 5.7421875 04 60 04 c6 04 d8 04 fc 00 00 03 8e 00 00 00 aa 5.76 5.85 5.94 05 00 05 14 05 28 00 00 00 00 00 00 6.0 6.2 6.5 6.552 05 35 05 61 05 a4 05 b0 05 55 0c 71 07 1c 00 00 6.6 6.65 6.8 05 ba 05 c5 05 e7 0a aa 0c 71 01 c7 7.02 06 18 00 00 7.2 06 40 00 00 7.38 06 68 00 00 7.56 06 90 00 00 msp 44x8g-c4 preliminary data sheet 86 march 29, 2004; 6251-623-1pd micronas 6.4.1. nicam mode control/additional data bits register nicam operation mode control bits and a[2:0] of the additional data bits. format: important: ?s? = bit[0] indicates correct nicam-syn- chronization (s = 1). if s = 0, the msp 4418/4458g has not yet synchronized correctly to frame and sequence, or has lost synchronization. the remaining read registers are therefore not valid. the msp mutes the nicam output automatically and tries to synchro- nize again as long as any nicam standard is selected by the standard select register. the operation mode is coded by c4-c1 as shown in table 6?10. note: it is not necessary to read out and evaluate the c_ad_bits. all evaluation is performed in the msp and indicated in the status register. 6.4.2. additional data bits register contains the remaining 8 of the 11 additional data bits. the additional data bits are not yet defined by the nicam 728 system. format: 6.4.3. cib bits register cib bits 1 and 2 (see nicam 728 specifications). format: 6.4.4. nicam erro r rate register average error rate of the nicam reception in a time interval of 182 ms, which shou ld be close to 0. the ini- tial and maximum value of error_rate is 2047. this value is also active if no nicam-standard is selected. since the value is achieved by filtering, a cer- tain transition time (approx. 0.5 sec) is unavoidable. acceptable audio may have error rates up to a value of 700 dec . individual evaluation of this value by the con- troller and an appropriate threshold may define the fall- back mode from nicam to fm/am-mono in case of poor nicam reception. the bit error rate per second (ber) can be calculated by means of the following formula: ber = error_rate * 12.3*10 ? 6 /s msb c_ad_bits 00 23 hex lsb 11...76543210 auto _fm ... a[2] a[1] a[0] c4 c3 c2 c1 s table 6?10: nicam operation modes as defined by the ebu nicam 728 specification c4 c3 c2 c1 operation mode 0000stereo sound (nicama/b), independent mono sound (fm1) 0001two in dependent mono signals (nicama, fm1) 0010three indepen dent mono channels (nicama, nicamb, fm1) 0011data transmission only; no audio 1000stereo sound (nicama/b), fm1 carries same channel 1001one mono si gnal (nicama). fm1 carries same channel as nicama 1010two ind ependent mono channels (nicama, nicamb). fm1 carries same channel as nicama 1011data transmission only; no audio x 1 x x unimplemented sound coding option (not yet defined by ebu nicam 728 specification) auto_fm: monitor bit for the auto_fm status: 0: nicam source is nicam 1: nicam source is fm msb add_bits 00 38 hex lsb 76543210 a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] msb cib_bits 00 3e hex lsb 76543210 xxxxxxcib1cib2 error_rate 00 57 hex error free 0000 hex maximum error rate 07ff hex preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 87 6.5. manual mode: description of dsp write registers 6.5.1. additional channel matrix modes this table shows additional modes for the channel matrix registers. the sum/difference mode can be used together with the quasi-peak detector to determine the sound mate- rial mode. if the difference signal on channel b (right) is near to zero, and the sum signal on channel a (left) is high, the incoming audio signal is mono. if there is a significant level on the difference signal, the incoming audio is stereo. 6.5.2. fm fixed deemphasis note: this register is initialized during standard selection and is automatically updated when automatic sound select (modus[0]=1) is on. 6.5.3. fm adaptive deemphasis note: this register is initialized during standard selection and is automatically updated when automatic sound select (modus[0]=1) is on. 6.5.4. nicam deemphasis a j17 deemphasis is always applied to the nicam sig- nal. it is not switchable. 6.5.5. identification mode for a2 stereo systems to shorten the response time of the identification algo- rithm after a program change between two fm-stereo capable programs, the reset of the ident-filter can be applied. sequence: 1. program change 2. reset ident-filter 3. set identification mode back to standard b/g or m 4. wait approx. 500 ms 5. read stereo detection register note: this register is initialized during standard selection and is automatically updated when automatic sound select (modus[0]=1) is on. main matrix 00 08 hex l aux matrix 00 09 hex l scart1 matrix 00 0a hex l scart2 matrix 00 41 hex l i 2 s matrix 00 0b hex l quasi-peak detector matrix 00 0c hex l mix1 00 38 hex l mix2 00 38 hex l i2s4 async output 00 46 hex l sum/diff 0100 0000 40 hex ab_xchange 0101 0000 50 hex phase_change_b 0110 0000 60 hex phase_change_a 0111 0000 70 hex a_only 1000 0000 80 hex b_only 1001 0000 90 hex fm deemphasis 00 0f hex h 50 s 0000 0000 00 hex reset 75 s 0000 0001 01 hex j17 0000 0100 04 hex off 0011 1111 3f hex fm adaptive deemphasis wp1 00 0f hex l off 0000 0000 00 hex reset wp1 0011 1111 3f hex identification mode 00 15 hex l standard b/g (german stereo) 0000 0000 00 hex reset standard m (korean stereo) 0000 0001 01 hex reset of ident-filter 0011 1111 3f hex msp 44x8g-c4 preliminary data sheet 88 march 29, 2004; 6251-623-1pd micronas 6.6. manual mode: description of dsp read registers all readable registers are 16-bit wide. transmissions via i 2 c bus have to take place in 16-bit words. some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. these registers are not writable. 6.6.1. stereo detection register for a2 stereo systems note: it is not necessary to read out and evaluate the a2 identification level. all evaluation is per- formed in the msp and indicated in the status register. 6.6.2. dc level register the dc level register measures the dc component of the incoming fm signals (fm1 and fm2). this can be used for seek functions in satellite receivers and for if fm frequencies fine tuning. if the dco frequency is lower than the actuel carrier frequency, the resulting dc level will be positive, an dvia versa. in the audio signal the dc content is suppressed. the time con- stant , defining the transition time of the dc level register, is approximately 28 ms. 6.7. demodulator source channels in manual mode 6.7.1. terrestrial sound standards table 6?11 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestrial sound standards. see table 2?2 for the assignment in the automatic sound select mode. in manual mode for terrestrial sound standards, only two demodulator sources are defined. 6.7.2. sat sound standards table 6?12 shows the source channel assignment of the demodulated signals for sat sound standards. stereo detection register 00 18 hex h stereo mode reading (two?s complement) mono near zero stereo positive value (ideal reception: 7f hex ) bilingual negative value (ideal reception: 80 hex) dc level readout fm1 (msp-ch2) 00 1b hex h + l dc level readout fm2 (msp-ch1) 00 1c hex h + l dc level [8000 hex ... 7fff hex ] values are 16 bit two?s complement preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 89 table 6?11: manual sound select mode for terrestrial sound standards source channels of sound select block broadcasted sound standard selected msp standard code broadcasted sound mode fm matrix fm/am (use 0 for channel select) stereo or a/b (use 1 for channel select) b/g-fm d/k-fm m-korea m-japan 03 04, 05 02 30 mono sound a mono mono mono stereo german stereo korean stereo stereo stereo bilingual, languages a and b no matrix left = a right = b left = a right = b b/g-nicam l-nicam i-nicam d/k-nicam d/k-nicam (with high deviation fm) 08 09 0a 0b 0c, 0d nicam not available or nicam error rate too high sound a mono 1) analog mono no sound with auto_fm: analog mono mono sound a mono 1) analog mono nicam mono stereo sound a mono 1) analog mono nicam stereo bilingual, languages a and b sound a mono 1) analog mono left = nicam a right = nicam b btsc 20 mono sound a mono mono mono stereo korean stereo stereo stereo mono + sap sound a mono mono mono stereo + sap korean stereo stereo stereo 21 mono sound a mono mono mono stereo mono + sap no matrix left = mono right = sap left = mono right = sap stereo + sap fm-radio 40 mono sound a mono mono mono stereo korean stereo stereo stereo 1) automatic refresh to sound a mono, do not writ e any other value to the register fm matrix! table 6?12: manual sound select modes for sat-reception (fm matrix is set automatically) source channels of sound select block for sat-modes broadcasted sound standard selected msp standard code broadcasted sound mode fm matrix fm/am (source select: 0) stereo or a/b (source select: 1) stereo or a (source select: 3) stereo or b (source select: 4) fm sat 6, 50 hex mono sound a mono mono mono mono mono 51 hex stereo no matrix stereo stereo stereo stereo bilingual no matrix left = a (fm1) right = b (fm2) left = a (fm1) right = b (fm2) a (fm1) b (fm2) msp 44x8g-c4 preliminary data sheet 90 march 29, 2004; 6251-623-1pd micronas 7. appendix c: application information 7.1. exclusions of audio baseband features in general, all functions can be switched independently. two exceptions exist: 1. nicam cannot be processed simultaneously with secondary channel (see fig. 2?3 and fig. 2?2 on page 12). 2. fm adaptive deemphasis cannot be processed simultaneously with fm-identification. 7.2. phase relationship of analog outputs the analog output signals: main, aux, and scart2 all have the same phases. the scart1 output has oppo- site phase. using the i 2 s-outputs for other dsps or d/a convert- ers, care must be taken to adjust for the correct phase. fig. 7?1: phase diagram of the msp 44x8g scart2-ch. scart1 scart1 scart2 scart4 scart3 mono main audio scart dsp input select scart output select baseband processing aux scart1-ch. scart2 i2s_out i2s_in1/2/3 mono, scart1...4 i2s4_out preliminary data sheet msp 44x8g-c4 micronas march 29, 2004; 6251-623-1pd 91 7.3. application circuit a sc1_out_l sc1_out_r sc2_out_l sc2_out_r ahvsup ahvss avsup dvsup dvss resetq avss vref1 vref2 5 v 5 v 8 v avss 5v 5v capl_m capl_a vreftop agndc ana_in1+ ana_in2+ ana_in- xtal_in xtal_out msp 44x8g d_ctr_i/o_0 d_ctr_i/o_1 aud_cl_out testen + 100 ? 100 ? 100 ? 100 ? 22 f 22 f 22 f 22 f + + + daca_r 1 nf 1 nf 1 nf 1 nf daca_l dacm_r dacm_l 1 f 1 f 1 f 1 f main channel tuner 1 tuner 2 sif 2 in signal gnd sif 1 in 56 pf 56 pf 56 pf + 3.3 f 100 nf 100 nf 10 f + if ana_in2+ 8v(5v) 18.432 mhz + + 10 f10 f mono_in sc1_in_l sc1_in_r asg sc2_in_l sc2_in_r asg sc3_in_l sc3_in_r asg sc4_in_l sc4_in_r standbyq adr_sel i2c_da i2c_cl i2s_ws4 i2s_cl4 i2s_da_out4 i2s_ws i2s_cl i2s_da_in1 i2s_da_in2/3 i2s_da_out 220 pf alternative circuit for sif-inputs for more attenuation of video 100 pf 56 pf 1 k ? ana_in1/2+ ahvss ahvss ahvss 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf 330 nf dvss dvss avss components: c s. section 4.6.2. resetq (from controller, see section 4.6.3.3.) 1.5 nf 470 pf 10 f 1.5 nf 470 pf 10 f 1.5 nf 470 pf 10 f i2s_da_in3 i2s_ws3 i2s_cl3 aux channel/ fm-modulator aux channel dvss ahvss (5 v) not used ahvss ahvss (3.3 v 1) ) 1) only available on request all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. msp 44x8g-c4 preliminary data sheet 92 march 29, 2004; 6251-623-1pd micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-623-1pd 8. appendix d: msp 44x8g version history msp 44x8g-a1 first release msp 44x8g-a2 ? j17 fm-deemphasis implemented ? input specification for resetq and testen changed msp 44x8g-b3 ? the automatic sound sele ct (ass) malfunction has been corrected. in the previous version, under cer- tain circumstances and depending on the processor load, e.g.: use of the asynchronous i 2 s3 interface, the automatic sound select feature (ass) did not work correctly. ? correction of 10 s delay between left and right: in case of any stereo output from the demodulator (fm/am, st or a/b) there was a constant time delay of 10 s between left and right channel in the a1 and a2 versions. ? correction of default scart-switch configuration dur- ing power-up ? correction of unstable sound mode detection when the msp reaches a specific higher case tempera- ture (occurs only in eia-j standard) ? correction of i 2 s output interface msp 44x8g-c4 ? asynchronous i 2 s output interface and related con- trol interfaces implemented ? astra digital radio (adr) no longer supported ? 3.3 v mode for dvsup2 available on request ? audio/video synchronization is only available if i 2 s4 sample length i2s4_wlen is set to 32 bit per sam- ple. 9. data sheet history 1. data sheet: ?msp 44x8g multistandard sound pro- cessor family?, june 16, 2003, 6251-516-1ds. first release of the data sheet. major changes: ? specification for version b3 added ? section 4.1.: diagrams for all packages changed ? plqfp64 changed to pmqfp64-2 2. preliminary data sheet: ?msp 44x8g-c4 multistan- dard sound processor family?, march 29, 2004, 6251-623-1pd. first release of the preliminary data sheet. major changes: ? new order no. for version c4 ? specification for version c4 added |
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